Samsung Electronics Co., Ltd.

Min-Joon Park

Chang-min Park

Cha-Won Koh

Jae-hong Park

Je-Woo Han

Gyung-Jin Min

Suk-Ho Joo

Jin-Young Park

Jun-ho Yoon

Kyung-rae Byun

Seok-Hyun Lim

Su-Hong Kim

A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50&#xb0; to about 80&#xb0;.

Methods of forming semiconductor device using bowing control layer

In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate.

Methods of forming patterns and methods of manufacturing semiconductor devices using the same

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Methods of forming fine patterns and methods of fabricating semiconductor devices

A plasma dry etching apparatus includes a pedestal in a process chamber, the pedestal being configured to support a wafer, a cathode electrode and a plate electrode in the process chamber, the cathode and plate electrodes being configured to apply radio-frequency (RF) power, an edge ring on an edge of the pedestal, a coupling ring having a first side on the pedestal and a second side on the edge ring, an edge cooling unit in the coupling ring, the edge cooling unit being configured to cool the edge ring to drop a temperature of an extreme edge of the wafer, and an edge heating unit in the coupling ring, the edge heating unit being configured to heat the edge ring to raise the temperature of an extreme edge of the wafer.

Plasma dry etching apparatus having coupling ring with cooling and heating units

Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

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Yongin-si, South Korea

Min-Joon Park