Samsung Electronics Co., Ltd.

Min Jae Oh

Ik Soo Kim

Ji Woon Im

Sang Ho Rha

A semiconductor memory device includes a cell substrate, a mold structure including a plurality of gate electrodes stacked on the cell substrate, the gate electrodes including a first ground selection line, a second ground selection line and a plurality of word lines, which are sequentially stacked, a channel structure that extends in a vertical direction that crosses an upper surface of the cell substrate and penetrates the mold structure, a partial isolation region that extends in a first direction that is parallel with the upper surface of the cell substrate and partially separates the mold structure, and a ground isolation structure that connects two partial isolation regions adjacent to each other in the first direction, extends in the vertical direction and penetrates the first ground selection line and the second ground selection line, wherein a width of the ground isolation structure increases with distance from the cell substrate.

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Hwaseong-si, South Korea

Min Jae Oh