National Semiconductor Corporation

Foveonics, Inc.

Foveon, Inc.

Min-hwa Chi

Albert M Bergemont

Carver A Mead

Hosam Haggag

Richard B Merrill

Chih Sieh Teng

Lih-Ying Ching

Chih-Sieh Teng

Gu-Fung David Tsuei

Tobi Delbruck

Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p&plus; contact region and the PLDD region in the control gate well of the conventional EPROM design. This is permitted because the V implant step is masked, permitting the control gate region to operate in accumulation mode during application of 5V programming voltages.

Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process

The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.

Method for forming a bipolar-based active pixel sensor cell with poly

An imaging array having overflow protection and electronic shuttering features is realized without an increase in pixel complexity. Overflow protection is provided by pulsing each row of the imager with a small overflow pulse during the sense amplifier reset phase. An electronic shutter is realized using a modified version of the pixel readout timing. The shutter provides sub-frame exposure by restricting the number of line-times a pixel is allowed to integrate. For a full-frame exposure, each pixel is read out once per frame; during readout of the other rows of the array, the pixel integrates. For subframe exposure, the pixel is continually reset, using a shutter pulse applied to the row lines during sense amplifier reset, until a certain number of rows (line-times) before it is to be read out. The pixel then is allowed to integrate until it is read out normally.

Capacitive coupled bipolar active pixel imager having overflow

Method for forming a bipolar-based active pixel sensor cell with metal

An active pixel image cell which includes a photosensor, active devices for control of the sensor and readout of a signal representing the intensity of light to which the sensor is exposed, and a neuron MOSFET transistor which 'both amplifies the signal from the photosensor and' simulates the behavior of a human neuron. An integrated neural network and imaging array may be formed by interconnecting a group of such pixels. Digital signal processing algorithms used for image processing may be implemented at the pixel level by appropriate interconnections between the output signals from the photosensor of surrounding pixels and the neuron MOSFET.

Neural network active pixel cell

Disclosed is a floating gate neuron MOS transistor that may be incorporated into devices such as low voltage silicon control rectifiers for protection of internal circuits against electrostatic discharge. The transistor includes two or more input gates capacitively coupled to the floating gate. By adjusting the coupling ratio of the input gates, it is possible to control the transistor drain turn-on voltage very precisely and thereby turn on the rectifier without relying on avalanche breakdown of the transistor.

ESD Input protection using a floating gate neuron MOSFET as a tunable

An active pixel image cell which includes a photosensor and an embedded memory element and may be used to produce signals corresponding to the photosensor outputs for successive frames. The structure of the active pixel cell includes an analog, non-volatile, or dynamic memory element and the control elements needed to store the output of the photosensor generated during a previous frame. The pixel elements then generate a signal representing the current frame output of the photosensor. The current frame output and previous frame output are then provided as output signals for the pixel and may be subjected to off-pixel processing as desired. For example, the two values may be subtracted from one another by an off-pixel difference amplifier to form a signal representing the difference between the image on the photodiode sensor of the pixel between successive frames. The difference signal may then be used for purposes of video compression, motion detection, or image stabilization.

Active pixel image cell with embedded memory and pixel level signal

A color active pixel sensor cell is formed by utilizing four photodiodes which are each covered with a layer of oxide. The thicknesses of the layers of oxide are set so that a first layer of oxide prohibits red light from entering the first photodiode, a second layer of oxide prohibits green light from entering the second photodiode, a third layer of oxide prohibits blue light from entering the third photodiode, and a fourth layer of oxide allows visible light to enter the fourth photodiode. The amount of red light received by the cell is then determined by subtracting the light energy collected by the first photodiode from the light energy collected by the fourth photodiode. Similarly, the amount of green and blue light received by the cell is determined by subtracting the light energy collected by the second and third photodiodes, respectively, from the amount of light energy collected by the fourth photodiode.

Color active pixel sensor cell with oxide color filter

A single-poly EPROM cell, which has spaced-apart regions of opposite conductivity formed in the base region and a thin layer of tunnel oxide, is formed in a triple-well CMOS-compatible process. By utilizing a triple-well structure and a thin layer of tunnel oxide, the cell of the present invention is both electrically programmable and erasable in a low-voltage, i.e., +3.3V environment.

Single-poly EEPROM cell that is programmable and erasable in a

A capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the 'shutter') which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.

Capacitor-coupled bipolar active pixel sensor with integrated electronic

A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.

Method for forming a mixed-signal CMOS circuit that includes

A high density EEPROM cell array structure utilizes a floating gate architecture for the access transistor and a double poly process in which the control gate and floating gate of both the access transistor and the memory cell are self-aligned, resulting in a much more compact cell than previously available. In addition, the process flow utilizes only two masks compared to the four mask flow utilized in the prior art. This leads to cost reduction in the fabrication process. The structure results in significantly reduced read time for the cell array.

High density EEPROM array using self-aligned control gate and floating

A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide.backslash.nitride.backslash.oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO.backslash.poly-1 sandwich is then anisotropically etched to form first and second stacks which provide the floating gate/control gate electrodes for the EEPROM cell access transistor and the EEPROM cell storage cell structure, respectively.

Method of fabricating a high density EEPROM cell

A MOS-based active pixel sensor cell utilizes the parasitic bipolar action of the cell to produce a horizontal current in lieu of the vertical image current associated with conventional bipolar-based active pixel sensor cells. Image data is collected during an integration period by applying a negative voltage to the gate of the MOS transistor which is sufficient to reverse-bias both the source/body and drain/body junctions. Following this, the image data is read out by raising the gate voltage such that the source/body junction remains reverse-biased, and the drain/body junction becomes forward-biased. Under these bias conditions, an amplified horizontal image current flows from the source, through the body, and out of the drain.

MOS-based active pixel sensor cell that utilizes the parasitic bipolar

A capacitor coupled contactless imager structure and method of manufacturing the structure results in a phototransistor that includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the imager phototransistor. Silicon dioxide separates the polysilicon emitter contact and exposed surfaces of the base region from a layer of poly2 about 500-600 .ANG. thick that is formed to cover the entire base region.

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Palo Alto, CA, United States of America

Min-hwa Chi