Samsung Electronics Co., Ltd.

Yonsei University

Min-ho Kwon

Wun-Ki Jung

Kwi-Sung Yoo

Dong-Hun Lee

Seog-Heon Ham

Seung-hyun Lim

Jae-Hong Kim

Jin-Ho Seo

Gun-Hee Han

Won-Ho Choi

Youngcheol Chae

Yong-Suk Choi

Kyo-Jin Choo

Yu-Jin Park

Ju-Hyun Ko

Chi-Ho Hwang

Young-Tae Jang

Woo-jin Jo

Sin-Hwan Lim

Jeong-Jin Roh

Jae-Jin Yeo

Jung-Yoon Lee

Sang-hyun Cho

An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.

Analog-to-digital converter and image sensor having the same

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Line memory device and image sensor including the same

A temperature sensor includes a band gap reference (BGR) circuit, a voltage generation unit and a digital CDS circuit. The band gap reference (BGR) circuit generates a reference voltage proportional to a temperature. The voltage generation unit generates a first voltage and a second voltage based on the reference voltage, where the first voltage and the second voltage are proportional to the temperature. The digital CDS circuit generates a digital signal corresponding to the temperature by performing a digital correlated double sampling (CDS) operation on the first voltage and the second voltage. The temperature sensor is able to detect a temperature accurately.

Temperature sensor and image sensor having the same

An analog-to-digital converter includes a modulation unit and a digital signal generation unit. The modulation unit is disposed corresponding to at least one column line, and sequentially perform delta-sigma modulation on an analog input signal and at least one residue voltage to generate digital bit stream signals. The analog input signal is input through the at least one column line. The at least one residue voltage is generated by performing the delta-sigma modulation on the analog input signal. The digital signal generation unit generates a digital signal corresponding to the analog input signal based on the digital bit stream signals.

Analog-to-digital converter and image sensor including the same

An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Offset canceling circuit, sampling circuit and image sensor

An image sensor includes a delta-sigma analog-to-digital converter (ADC) including a delta-sigma modulator (DSM) and a voltage adjusting circuit. The DSM is configured to perform delta-sigma modulation on an analog signal from a unit pixel. The delta-sigma ADC is configured to convert the analog signal to a digital signal. The voltage adjusting circuit includes a replica inverter having a same configuration as at least one inverter included in the DSM. The voltage adjusting circuit is configured to adjust a power supply voltage and an input voltage provided to the at least one inverter based on a current flowing in the replica inverter.

Image sensors and image processing systems

An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.

Analog-to-digital converter having a comparison signal generation unit and image sensor including the same

Provided are a pixel sensor array and a complementary metal-oxide semiconductor (CMOS) image sensor including the same. The pixel sensor array includes a photoelectric transformation element configured to generate electric charges in response to incident light. A signal transmitting circuit is configured to output the electric charges accumulated in the photoelectric transformation element to a first node based on a first control signal, change an electric potential of the first node to an electric potential of a second signal line based on a second control signal, and output a signal sensed in the first node to a first signal line based on a third control signal. A switch element is configured to connect a supply power terminal to the second signal line based on a fourth control signal. A comparator connected to the first signal line and the second signal line and configured to compare a voltage of the signal and a voltage of a reference signal.

Pixel sensor array including comparator and image sensor including the same

A time-interleaved bandpass delta-sigma modulator is developed which includes a first adder and a second adder and a comparator. An input signal is transmitted to the first adder according to the clock frequency of each channel block, and an n channel block output uof the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output vof the second adder is transmitted to the second adder of an n+2 block, and an output ythat passes through an n block comparator is transmitted to the first adder and the second adder of an n+2 block. Therefore, a modulator sequentially receives output from the comparator of each block for generating the final output y.

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Seoul, South Korea

Min-ho Kwon