Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Daewoong Pharmaceutical Co., Ltd.

Semes Co., Ltd.

Hyundai Steel Company

Ilhwa Co., Ltd.

Skhynix Inc.

Sungkyunkwan University

Industry-University Cooperation Foundation Hanyang University

Dong-a University Research Foundation for Industry-academy Cooperation

Kia Motors Company

Ap Systems Inc.

Min Hee Cho

Wonsok Lee

Satoru Yamada

Hui-Jung Kim

Woo Bin Song

Kiseok Lee

Junsoo Kim

Min Tae Ryu

Yoosang Hwang

Sang Woo Lee

Jun Soo Kim

Minsu Lee

Won Sok Lee

Bong-Soo Kim

Jin Ho Hwang

Joon Seok Park

Hyunmog Park

Ki Chun Lee

Jae Ho Hong

Sung Yeup Chung

Youn Jung Yoon

Dong Cheol Park

Seok Gyu Sonh

Ho Bin Lee

Yong Kim

Tae Young Kim

Mirco Cantoro

Sungwon Yoo

Ji Duck Kim

Hui Jung Kim

Hei Seung Kim

Moon Young Jeong

Ja Kyung Yoo

Beomyong Hwang

Kyeong Min Lee

Ki Jae Hur

Tae-Keun Kim

Jong Hwan Sung

Nam Ho Jeon

Il Gyu Kim

Seung Ho Lee

Jun Hee Lee

Kyunghwan Lee

Yongseok Kim

Keunnam Kim

Dae Ig Jung

Dong Il Bae

Yongjin Lee

Sung Hoon Kim

Jung-Min Oh

Young-Hoo Kim

Dongsoo Woo

Kyung Hwan Lee

Sang Woo Park

Dongoh Kim

Seung Hyeok Chang

Byoung Hee Lee

Sung Wook Cho

In Woo Kim

Ha Young Kim

Ki Seok Lee

Moonyoung Jeong

Hyun Mog Park

Minwoo Song

Sung-Sam Lee

Jae Yong Lee

Min Su Lee

Ji Ah Kim

Hyeoungwon Seo

Chunhyung Chung

Kyo-Suk Chae

Jae Kyeong Jeong

Kyoung In Lee

Hyoung Shin

Taehyun An

Min Woo Song

Namho Jeon

Sang Hoon Uhm

Mi Ryeong Han

Hyun-Sil Oh

Sun Ah Jun

Yong Chae Kim

Jae Do Nam

Hyoshin Ahn

Ungryeol Lee

Bong Yong Lee

Seong Hyeon Lee

Kang Sul Kim

Hyeon Joo Seul

Chang Min Park

Hyo San Lee

Ji Soo Jeong

Yun Soo Yoon

Ye Rim Yeon

Honglae Park

Joohyun Jeon

Hyo Shin Kim

Youngjin Kang

Myeonggeun Kim

Tae Keun Kim

A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

Semiconductor memory device

A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

Semiconductor memory device including symmetrical channel patterns and wordlines

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

Semiconductor memory device having a confinement layer with a two-dimensional electron gas in the confinement layer

Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.

Semiconductor memory device having shield layer between peripheral circuit and cell array structures

A semiconductor memory device includes a cell area and a peripheral area, a base insulating layer including opposed first front and rear surfaces in the cell area, a first semiconductor substrate including opposed second front and rear surfaces in the peripheral area, an active pattern on the first front surface, a first conductive line extending in a first direction on a side of the active pattern, a capacitor structure on the active pattern, a first circuit element on the second front surface, and a second conductive line extending in a second direction intersecting the first direction on the first rear surface and the second rear surface. The active pattern extends in a vertical direction intersecting the first direction and the second direction to electrically connect the second conductive line to the capacitor structure.

Semiconductor memory device and method for fabricating the same

A substrate treating method including removing particles formed on a substrate by continuously performing a process of supplying a treatment liquid including a polymer and a solvent onto the substrate, forming a solidified liquid film by volatilizing the solvent in the treatment liquid, removing the solidified liquid film from the substrate by supplying a stripping liquid onto the substrate, and supplying a rinse liquid onto the substrate may be provided.

Substrate treating apparatus and substrate treating method

A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

Semiconductor memory device and a method of fabricating the same

Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

Semiconductor device including oxide semiconductor layer

The inventive concept provides a substrate treating method. The substrate treating method includes supplying a dissolving solution onto a rotating substrate; and supplying, after the supplying a dissolution solution, a treating liquid including a polymer onto the rotating substrate to form a liquid film.

Method for treating a substrate

A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

Semiconductor memory devices and methods for fabricating the same

Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

Memory devices

Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

Semiconductor memory devices

A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

Growing community of inventors

Suwon-si, South Korea

Min Hee Cho