Hynix Semiconductor Inc.

Skhynix Inc.

Min-Gyu Sung

Kwan-Yong Lim

Heung-Jae Cho

Yong-Soo Kim

Hong-Seon Yang

Se-Aug Jang

Tae-Yoon Kim

Tae-Kyung Kim

Sook-Joo Kim

Seung-Ryong Lee

Dong-Sun Sheen

Kwon Hong

Deok-Sin Kil

Seung-Ho Pyi

Tae-Kwon Lee

Won Kim

A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.

Semiconductor device having vertical channel transistor and method for fabricating the same

A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

Semiconductor device with gate stack structure

A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

Dual polysilicon gate of a semiconductor device with a multi-plane channel

A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar.

Transistor having vertical channel

A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten layer.

Method for fabricating tungsten line and method for fabricating gate of semiconductor device using the same

A method for fabricating a resistive memory device includes forming a lower electrode including a metal nitride layer over a substrate, forming a metal oxide layer used as a variable resistance material by oxidizing a part of the metal nitride layer, and forming an upper electrode on the metal oxide layer.

Method for fabricating resistive memory device

A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.

Semiconductor memory device

A semiconductor device includes a lower electrode, a variable resistance layer disposed over the lower electrode, the variable resistance layer is included a reactive metal layer being interposed between a plurality of oxide resistive layers and an upper electrode disposed over the variable resistance layer.

Semiconductor device and method for fabricating the same

A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each wordline from the gate electrode.

Semiconductor device with vertical channel transistor and low sheet resistance and method for fabricating the same

A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.

Transistor including bulb-type recess channel and method for fabricating the same

A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

Semiconductor device with gate structure

In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.

Growing community of inventors

Ichon-shi, South Korea

Min-Gyu Sung