Globalfoundries Inc.

Varian Semiconductor Equipment Associates, Inc.

International Business Machines Corporation

Applied Materials, Inc.

Globalfoundries U.S. Inc.

Min Gyu Sung

Ruilong Xie

Chanro Park

Hoon Sik Kim

Sony Varghese

Julien Frougier

Kwan-Yong Lim

Johannes M Van Meer

Kangguo Cheng

Naushad K Variam

Jae Young Lee

Lars W Liebmann

Steven J Bentley

Catherine B Labelle

Sukwon Hong

Ryan Ryoung-Han Kim

Hui Zang

Soon-Cheon Seo

John J Hautala

Morgan Evans

Anthony Renau

Rajesh Prasad

Puneet Harischandra Suvarna

Tek Po Rinus Lee

Brent A Anderson

Junli Wang

Heng Wu

Joseph C Olson

Hiroaki Niimi

Su Chen Fan

Laertis Economikos

Daniel Chanemougame

Haigou Huang

Murat Kerem Akarvardar

Lei Sun

Wenhui Wang

Nigel Graeme Cave

Christopher Michael Prindle

Jun Seok Lee

Dong-Ick Lee

Neeraj Tripathi

Kwanyong Lim

Edward J Nowak

Tenko Yamashita

Juntao Li

Takashi Ando

Nicolas J Loubet

Oleg Gluschenkov

Ajey Poovannummoottil Jacob

John H Zhang

Ruqiang Bao

Injo Ok

Haiting Wang

Xunyuan Zhang

Siva P Adusumilli

Kisik Choi

Guillaume Bouche

Xuefeng Liu

Xusheng Kevin Wu

Jiehui Shu

Cheng Chi

Bipul C Paul

Vimal Kumar Kamineni

Yi Qi

William James Taylor, Jr

Andre P Labonte

Jay William Strane

Andreas Knorr

Steven R Soss

Hsien-Ching Lo

Guowei Xu

Steven Robert Sherman

Jia Zeng

Shao Beng Law

Xuelian Zhu

Andrew Gaul

Tassie Andersen

Yongiun Shi

Curtis S Durfee

Mary Claire Micaller Silvestre

A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Heterogeneous gate all around dielectric thickness

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor

A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Semiconductor backside contact structure with increased contact area

A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Semiconductor structure with wrapped-around backside contact

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.

Full wrap around backside contact

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.

Scaled 2T DRAM

A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

Spin-based gate-all-around transistors

A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Resistive random-access memory structures with stacked transistors

A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolation pillar structure located between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. The upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.

Isolation pillar structures for stacked device structures

Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.

Stacked field-effect transistors

Embodiments of present invention provide a ferroelectric random-access memory (FeRAM) cell. The FeRAM cell includes a vertical channel between a bottom source/drain region and a top source/drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, wherein the ferroelectric layer has two or more sections of different horizontal thicknesses between the bottom source/drain region and the top source/drain region. A method of manufacturing the FeRAM cell is also provided.

Ferroelectric random-access memory cell

Embodiments of present invention provide a resistive random-access memory (RRAM) cell. The RRAM cell includes a bottom electrode; a metal oxide layer, the metal oxide layer having a central portion that is in direct contact with the bottom electrode, a peripheral portion that is nonplanar with the central portion, and a vertical portion between the central portion and the peripheral portion; and a top electrode directly above the metal oxide layer. A method of manufacturing the RRAM cell is also provided.

RRAM with high work function cap

A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.

Tunable resistive random access memory cell

Growing community of inventors

Latham, NY, United States of America

Min Gyu Sung