Lg Semicon Co., Ltd.

Dongbu Electronics, Co. Ltd.

Hyundai Electronics Industries Co. Ltd.

Dongbu Anam Semiconductor, Inc.

Min Gyu Lim

Sung Chul Lee

Eun Jeong Park

The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes: a substrate where a memory cell array region and a segment select region are defined; first and second trenches respectively formed at the outer portion of the memory cell array region and at the outer portion of a buried layer formation region of the segment select region; an element isolating film and an isolating pattern respectively filling up the first and second trenches; a plurality of buried layers aligned on the substrate in a first direction by a predetermined interval, and surrounded by the isolating pattern; and a plurality of gates aligned in a second direction to cross the buried layers in an orthogonal direction.

Mask ROM, and fabrication method thereof

A method that includes: providing a substrate where a memory cell array region and a peripheral region are defined; forming a buried layer on the substrate; forming a gate material by positioning a gate insulating film on the substrate having the buried layer; forming first gates by covering the peripheral region, and etching the gate material of the memory cell array region according to a photolithography process; forming an insulating pattern on the substrate to fill up a space between the first gates and expose the surfaces of the first gates; forming second gates by covering the memory cell array region, and etching the gate material of the peripheral region according to the photolithography process; and forming a low resistance layer on the first gates, and simultaneously forming a source/drain at both sides of the second gates, by doping an impurity to the substrate having the first and second gates.

Method for fabricating mask ROM

Semiconductor memory and a method for fabricating the same, in which sides of a floating gate is formed to have a streamlined profile, for improving a device performance, the semiconductor memory including a semiconductor substrate, a plurality of field oxide films formed at fixed intervals in one direction for isolating an active region between adjacent field oxide films, a plurality of control gates formed at fixed intervals in a second direction perpendicular to the field oxide films, a plurality of floating gates respectively formed under the control gates spaced a distance from each other each having edge portions in the second direction with moderate slopes, an interlayer insulating layer formed at interfaces between the floating gate and the control gate, and source/drain formed in surfaces of a semiconductor substrate on both sides of the control gate.

Semiconductor memory and method for fabricating the same

A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.

Method for making flash memory

A non-volatile memory device includes a substrate, a projection having two sides formed on the substrate, a floating gate formed on the projection, a control gate formed on the substrate including the floating gate, a first impurity region formed in the substrate extended from one side of the projection, and a second impurity region formed in the substrate at the other side of the projection and in the substrate extended from the other side of the projection.

Device and fabricating method of non-volatile memory

A semiconductor device having a recessed channel structure which has a semiconductor region positioned at a level above a channel region, including a first conduction type substrate having a channel region therein, a second conduction type semiconductor region formed on the substrate excluding the channel region, a first insulation film formed on the semiconductor region, a second insulation film formed on a surface between the channel region and the semiconductor region, a first gate formed on a gate insulation film on the channel region, and a dielectric film formed between the first gate and the first insulation film. Also, a method for fabricating a semiconductor device having a recessed structure, including the steps of: forming a second conduction type polysilicon film on a first conduction type substrate; forming a first insulation film on the polysilicon film; forming a semiconductor layer by etching the first insulation film and the underlying polysilicon film; forming a second insulation film on an exposed surface of the substrate between the semiconductor layer and at sides of the semiconductor layer and the first insulation film; forming a first gate on the second insulation film; forming a dielectric film on a surface between the first gate and the second insulation film; and forming a second gate on the dielectric film.

Growing community of inventors

Chungcheongbuk-do, South Korea

Min Gyu Lim