International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Min Chul Sun

Randy William Mann

Oliver Desmond Patterson

Scott Jansen

Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Growing community of inventors

Hwasung-si, South Korea

Min Chul Sun