Samsung Electronics Co., Ltd.

Min-Chul Park

Changwook Jeong

Sanghoon Myung

Hyunjae Jang

In Huh

Jisu Ryu

Hyeon Kyun Noh

Hyungtae Kim

Young-Gu Kim

Keun-Ho Lee

Young-jin Choi

Seunguk Han

Namho Jeon

Seung-Uk Han

Je-Hyun Lee

Nam-Ho Jeon

Jeonghoon Ko

Min Chul Jeon

Ami Ma

Yunrong Li

Jeong-Hoon Ko

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

Simulation system for semiconductor process and simulation method thereof

A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

Semiconductor wafer fault analysis system and operation method thereof

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Semiconductor fault analysis device and fault analysis method thereof

A thickness of a first layer in a structure may be measured based on an original image of the structure. A first boundary of the first layer may be identified in the original image. A second boundary that is substantially indistinguishable in the original image may be identified based on converting the original image into a first image based on the first boundary and generating a second image based on filtering the first image. The first image may be generated based on adjusting partial image portions of the original image to align the representation of the first boundary with an axis line, such that the first image includes a representation of the first boundary that extends substantially in parallel with the axis line. The second boundary may be identified from the second image, and the thickness of the layer may be determined based on the identified first and second boundaries.

Method of measuring thickness, method of processing image and electronic system performing the same

A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.

Semiconductor device

Semiconductor devices are provided including a gate across an active region of a substrate; a source region and a drain region in the active region on either side of the gate and spaced apart from each other; a main channel impurity region in the active region between the source and drain regions and having a first channel impurity concentration; and a lightly doped channel impurity region in the active region adjacent to the drain region. The lightly doped channel impurity region has the same conductivity type as the main channel impurity region and a second channel impurity concentration, lower than the first channel impurity concentration. The lightly doped channel impurity region and the main channel impurity region contain a first element. The lightly doped channel impurity region also contains a second element, which is a different Group element from the first element.

Semiconductor devices having lightly doped channel impurity regions

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Hwaseong-si, South Korea

Min-Chul Park