Korea Airports Corporation

Adtechnology Co., Ltd.

Min Chul Jung

Young Seung Kim

Seung Moon Yoo

Jun Suk Kim

Keum Sik Yu

Scott Seungmoon Yoo

Hyung Kyu Woo

Dong Hee Koh

A memory device may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and an aligner that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data.

Memory device with data mergers and aligner

A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

Memory device, and method for driving memory

An aeronautical light aid for a vertical takeoff and landing (VTOL) flying object is provided. The aeronautical light aid includes a plurality of first lighting portions buried in a takeoff and landing port and configured to radiate light in a vertically upward direction, a plurality of second lighting portions provided on an outer side of the takeoff and lighting port and configured to radiate light in an externally upward direction, and a landing guide provided at the center of the takeoff and landing port.

Aeronautical light aid for vertical takeoff and landing

Disclosed herein is a latch circuit capable of preventing an output failure caused due to simultaneous transition of a control signal and an input signal. The latch circuit according to the present invention generates a separate control adjustment signal CTR using the control signal Control and the input signal In and uses the control adjustment signal CTR, instead of the control signal for a latch operation. Accordingly, when the control signal and the input signal transition at the same time, the control adjustment signal is processed not to transition during a transition interval of the input signal, thereby preventing a metastability problem that occurred in the existing latch circuit.

Growing community of inventors

Seoul, South Korea

Min Chul Jung