United Microelectronics Corp.

Min-Chuan Tsai

Hsin-Fu Huang

Chi-Mao Hsu

Chin-Fu Lin

Chien-Hao Chen

Wei-Yu Chen

Chun-Chieh Chiu

Wei-Chuan Tsai

Li-Han Chen

Kuo-Chih Lai

Tsun-Min Cheng

Pin-Hong Chen

Kuo-Chin Hung

Chi-Yuan Sun

Nien-Ting Ho

Chia-Chang Hsu

Chun-Tsen Lu

Yen-Tsai Yi

Tzung-Ying Lee

Ya-Hsueh Hsieh

Chih-Chien Liu

Chan-Lon Yang

Chun-Yuan Wu

Kun-Hsien Lin

Kun-Ju Li

Ching-Ling Lin

Shao-Wei Wang

Fu-Shou Tsai

Chia Chang Hsu

Li-Chieh Hsu

Jen-Chieh Lin

Shu Min Huang

Min-Hsien Chen

Mon-Sen Lin

Yi-Han Liao

Jing-Gang Li

Jian-Hong Su

Pei-Ying Li

Teng-Chun Tsai

Yi-Wei Chen

Chien-Ting Lin

Shih-Fang Tzou

Chia-Lin Hsu

Yen-Chen Chen

Tzyy-Ming Cheng

Zhi-Cheng Lee

Che-Hua Hsu

Yi-Wen Chen

Po-Cheng Huang

Cheng-Guo Chen

Shih-Min Chou

Po-Jui Liao

Jie-Ning Yang

Shao-Hua Hsu

Yang-Ju Lu

Guang-Yaw Hwang

Jui-Ming Yang

Hsiang-Chieh Yen

Tsung-Lung Tsai

Ching-Yun Chang

Yun-Tzu Chang

Hung-Ling Shih

Jung-Tsung Tseng

Shu-Min Huang

Chun-Lin Chen

Kun Ju Li

Hsin Jung Liu

Yi Han Liao

A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

Conductive structure and method for manufacturing conductive structure

A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

Manufacturing method of metal gate structure

A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

Conductive layout structure including high resistive layer

A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Semiconductor process for forming plug

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Semiconductor process

A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

Conductive structure having an entrenched high resistive layer

Semiconductor process and semiconductor device

A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.

Fabricating method of semiconductor structure

Semiconductor structure and process for forming plug including layer with pulled back sidewall part

A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.

Structure of metal gate structure and manufacturing method of the same

The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

Semiconductor device with a contact plug and method of fabricating the same

A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.

Method of forming contact strucutre

A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Method for filling trench with metal layer and semiconductor structure formed by using the same

A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Metal gate forming process

Growing community of inventors

Taipei, Taiwan

Min-Chuan Tsai