Integrated Device Technology, Inc.

Renesas Electronics America Inc.

Min Chu

Jagdeep Singh Bal

John C Hsu

Ron Wade

Pak-Kim Lau

A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref) to a second reference clock (ref) by entering holdover mode (), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider () that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.

Feedback control for accurate signal generation

A time-to-digital converter obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

Apparatus and methods for automatic time measurements

A multi-stop time-to-digital converter (TDC,) includes single-stop TDCs () connected to output nodes of a ring oscillator (). Other features and embodiments are also provided.

Use of ring oscillators for multi-stop time measurements

An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following:

Buffer with programmable input/output phase relationship

An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal. The calibration circuit also includes a selection block for performing a convergence test using the counted number of fast clock cycles, N, and M. The selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.

Calibration method and apparatus for phase locked loop circuit

A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.

High-speed programmable frequency divider with 50% output duty cycle

Methods and apparatuses are described to reduce phase noise in a low noise fractional reference-injection phase locked loop (FRIPLL). The FRIPLL includes a ring voltage controlled oscillator (VCO). An output of the ring VCO is input to a fractional interpolative frequency divider (FIFD). A signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD. The signal comparison circuit produces a control voltage signal in response to a phase difference between the reference clock signal and the further delayed output of the FIFD. The control voltage signal is input to the ring VCO to control a ring VCO frequency. An oscillator control circuit has a first input and a second input. The first input is a first delayed output of the FIFD. The second input is the reference clock signal. The oscillator control circuit generates a realignment signal which is used to realign a state transition in a ring VCO output signal to the reference clock signal when the ring VCO output signal is in a low state. Realignment occurs repeatedly at a frequency of the reference clock signal.

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Milpitas, CA, United States of America

Min Chu