United Microelectronics Corp.

Other

Smile Technology Co., Ltd.

Min-Chih John Hsuan

Charlie Han

Cheng-Te Lin

Li-Che Chen

Kai-Kuang Ho

Jerry Jaw

Tsung-Hsi Ko

Kun-Chih Wang

Hermen Liu

Fu-Tai Liou

Kuo-Ming Chen

Kuang-Hui Tang

Yu-Han Huang

Kelvin Yi-Tse Lai

Paul Chen

Taisheng Feng

Tazsheng Feng

Cheng-ju Hsieh

Tung-Chi Liu

A cartridge is adapted to be inserted removably into a drain hole of a urinal, and includes a cartridge body, a guide plate member, a detecting module and a filter unit. The cartridge body has an internal space having an opening. The guide plate member is disposed in the opening, and is perforated to guide liquid which exits the urinal via the drain hole to flow therethrough into the internal space. The detecting module includes a drug-detecting chip for detecting presence of a specified drug, and a controlling chip for controlling operation of the drug-detecting chip according to measured displacement of the guide plate member. The filter unit utilizes a channel to direct the liquid from

Urinal cartridge and urinal having the same

The present invention relates to an attachment device for micro devices, comprising a main body and an attachment member seat in connection with the main body. The main body provides a receiving space to accommodate a functional module element. The attachment member seat provides a cavity to accommodate at least one attachment member to attach the attachment device to an article. A wearable micro device comprising the functional module element and the attachment device is also disclosed.

Attachment device for micro devices and wearable micro devices having the attachment device

A local detection processing system includes a local detection processing device and at least two types of detectors. The detectors are disposed in an area for detecting properties or property changes of a specific target to generate a detection signal. The local detection processing device analyzes the detection signals and transmits the detection result to a processing center. The local detection processing device includes a detection information receiving unit receiving the detection signals generated by the at least two types of detectors; a memory unit recording codes of the at least two types of detectors, a format of the detection signal, information of the corresponding processing center and values of the detection signals; an information processing unit analyzing the received detection signals, determining a detection result whether to transmit the detection result and the processing center; and a communication unit connecting at least two processing centers.

Local detection processing device and system

A portable information detection and processing device includes an information detection unit, for detecting information recorded by at least one functional element; a memory unit, for recording recognition data of the at least one functional element and information detected by the functional element; a display unit, for displaying the recognition data of the functional element and the information recorded by the functional element; and an information processing unit, connected to the information detection unit, the memory unit and the display unit, for processing the recognition data of the functional element and the information detected by the functional element, and controlling the information detection unit, the memory unit and the display unit.

Portable information detection and processing device and system

A manufacturing method of a wafer level chip scale package of an image-sensing module is provided. The method includes providing a wafer having a plurality of die regions, and a plurality of sensing units is formed on a surface of the wafer in each die region. A plurality of lens units is formed on the sensing units, wherein each lens unit includes a lens and an edge wall that are integrally formed. A light-shielding film is also formed on a surface of at least one edge wall of at least one lens units. A dicing process is then performed on the wafer to form a plurality of image sensor chips.

Manufacturing method of wafer level chip scale package of image-sensing module

An image-sensing module is provided. The image-sensing module includes a substrate, a plurality of image-sensing units, a plurality of micro lenses and a focusing unit. The image-sensing units are disposed on the substrate and the micro lenses are respectively disposed on one of the image-sensing units. The focusing unit is disposed on the substrate and covers the micro lenses. A top surface of the focusing unit is a curved surface. Furthermore, a method of manufacturing the image-sensing module and an image capture apparatus are provided.

Image-sensing module of image capture apparatus and manufacturing method thereof

A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.

Chip packaging process

An integrated audio/video sensor is provided. The integrated sensor comprises an image-receiving module for sensing a light of an image, a sound-receiving module for sensing a sound and a signal-transforming module for integrating image and sound signals into an audio/video signal. The integrated sensor integrates image and sound together simultaneously and synchronously. Furthermore, the integrated sensor can be connected directly to an image-processing system. The integrated sensor not only provides excellent synchronization of audio and video signals, but also reduces the size and cost of producing the integrated sensor as well.

Integrated audio/video sensor

A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Ultra-thin wafer level stack packaging method

A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, a through-hole via formed as part of the interconnect is filled with an inert material during operations associated with subsequent active device formation on such die.

Integrated circuit with improved interconnect structure and process for making same

The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Method for manufacturing wafer level chip scale package structure

Intermediate structure for making integrated circuit device and wafer

An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals. During fabrication, the replacement of defective chips with spare chips is accomplished by using two extra conductive layers and patterning the extra layers using a mask that is independent of the defect distribution of a particular wafer.

Placement and routing for wafer scale memory

A method of fabricating a direct contact through hole type wafer. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads, which couples with the multilevel interconnects, are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.

Growing community of inventors

Hsinchu, Taiwan

Min-Chih John Hsuan