Taiwan Semiconductor Manufacturing Comp. Ltd.

Min-Chien Hsiao

Chao-Wen Shih

Chen-Hua Douglas Yu

Nien-Fang Wu

Shou-Zen Chang

Chung-Shi Liu

Ming-Fa Chen

Sung-Feng Yeh

Tzuan-Horng Liu

Hao-Yi Tsai

Mirng-Ji Lii

Hung-Yi Kuo

Tsung-Yuan Yu

Yung-Ping Chiang

Yi-Che Chiang

Chuei-Tang Wang

Han-Ping Pu

Chieh-Yen Chen

Chuan-An Cheng

A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

Methods of fabricating package structure

Methods of fabricating the same die stack structure and semiconductor structure

Die stack structure, semiconductor structure and method of fabricating the same

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.

Chip package with antenna element

Semiconductor structure and method of fabricating the same

A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.

Package structure and manufacturing method thereof

In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

Package structure, electronic device and method of fabricating package structure

The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

Semiconductor structure and method manufacturing the same

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.

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Taichung, Taiwan

Min-Chien Hsiao