Taiwan Semiconductor Manufacturing Comp. Ltd.

Min-Chie Jeng

Hsiao-Tsung Yen

Chin-Wei Kuo

Yu-Ling Lin

Ho-Hsiang Chen

Jhe-Ching Lu

Cheng-Wei Luo

Ke-Wei Su

Cheng Yuan Hsiao

Chewn-Pu Jou

Huan-Neng Chen

Mei-Show Chen

Chung-Kai Lin

Yi-Shun Huang

Juan Yi Chen

Tzuan-Horng Liu

Katherine H Chiang

Hsien-Pin Hu

Chung-Yu Lu

Lester Chang

Victor Chih Yuan Chang

Chang-Yu Huang

Ya-Chin Liang

Jun-Cheng Huang

Jia-Lin Lo

Feng-Ling Hsiao

Wai-Kit Lee

Cheng Hung Lee

Tzu-Jin Yeh

Yi-Chun Chen

Wen-Sheh Huang

Cheng-Hung Lee

Chih-Yuan Chang

Hsiu-Ying Cho

Sally Liu

Li-Chung Hsu

Ting-Sheng Huang

Jiun-Kai Huang

Yu-Ling Yu

Chen-Ming Tsai

Juan-Yi Chen

Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.

Method of forming semiconductor package transmission lines with micro-bump lines

An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

Filter and capacitor using redistribution layer and micro bump layer

A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.

Semiconductor structure

A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.

Compact vertical inductors extending in vertical planes

An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Method and system for integrated circuit design with on-chip variation and spatial correlation

Methods and apparatus for transmission lines in packages

A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

Method for establishing aging model of device and analyzing aging state of device with aging model

A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.

Simulation scheme including self heating effect

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Taipei, Taiwan

Min-Chie Jeng