Samsung Electronics Co., Ltd.

Min Cheol An

Do Soo Jeong

Bo Hyun Shin

Hyeon J Jeong

Seung H Ahn

Ki Won Choi

Jung Hwan Cuun

Yooung D Kweon

A printed circuit board (PCB) for use in chip-on-board (COB) packages reduces failures due to warping of the COB packages. The PCB includes a board body having a upper surface and a lower surface, a chip bonding area on the upper surface for attaching a semiconductor device, and a plurality of conductors in a circuit pattern on the upper surface outside the chip bonding area, for electrical connection to the semiconductor device using a plurality of bonding wires. An encapsulation region encloses the chip bonding area, the bonding wires, a portion of the plurality of conductors, and a portion of the upper surface. The board includes external contacts on the lower surface for electrical connections to an external electrical appliance, and via holes through the board body for electrically connecting the plurality of conductors in the circuit pattern to the external contacts. A plurality of volume-adjusting regions, on the upper surface outside the chip bonding area and inside the encapsulation region, adjust a volume of a molding compound in the final package.

Printed circuit board and chip-on-board packages using same

A base card improves the mounting reliability of a COB package particularly when the package has molding by-products such as epoxy burrs or molding flashes. The base card has a COB package receiving part made up of first and second sections. The receiving part is stepped so that the sections thereof have shapes that are complementary to that of and for receiving a peripheral portion of the printed circuit board of the COB package and the package body the COB package, respectively. The second section has a bevel at the transition of the first section into the second section. This bevel helps define a space in which the by-products are accommodated when the COB package is mounted to the base card. Further, the second section of the COB package receiving part may define an opening in the bottom surface of the base card. This opening also prevents damage to the base card by preventing the need for the bottom of the package body to bear against the bottom of the base card when the COB package is mounted to the base card.

Base cards and IC cards using the same

A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device. The leads of the upper lead frame are formed to directly contact top surfaces of the inner leads of the lower lead frame, so that the upper and the lower parts can be electrically interconnected. An insulating adhesive film is interposed between the upper semiconductor chip and the inner leads of the lower lead frame.

Stacked chip package device employing a plurality of lead on chip type

A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, each individual semiconductor device including (1) a semiconductor chip, (2) a protective body for encapsulating the semiconductor chip, (3) a lead frame comprising inner lead portions electrically interconnected to the semiconductor chip and included within the protective body, outer lead portions formed as a single body with the inner lead portions, and coupling lead portions located between the inner and outer lead portions and having a top surface exposed upward from the protective body, and (4) a plurality of vertical interconnection elements attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions, whereby, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnection elements, and electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

Three dimensional stack package device having exposed coupling lead

An arrangement for vertically mounting a semiconductor device to a substrate, e.g., a printed circuit board (PCB), in which a plurality of sequentially arranged external leads of the semiconductor device include at least three different sets of non-consecutive ones of the external leads which have laterally outwardly extending foot portions lying in respective, vertically spaced-apart planes, and in which the foot portions of first and second ones of the sets of non-consecutive external leads are respectively secured to respective first and second steps formed in one of a plurality of walls defining a cavity in the PCB, and a third set of the non-consecutive external leads are secured to a portion of a major surface of the PCB adjacent the cavity.

Growing community of inventors

Suwon, South Korea

Min Cheol An