National Applied Research Laboratories

Chang Gung University

Min-Cheng Chen

Chia-Yi Lin

Hou-Yu Chen

Chia-Hua Ho

Jia-Min Shieh

Mu-Yi Hua

Rung-Ywan Tsai

Hsiao-Chien Chen

Wen-Kuan Yeh

Kai-Shin Li

Yi-Ting Chen

Bo-Wei Wu

Chang-Hsien Lin

Tung-Yen Lai

Chien-Lun Chen

A reduced graphene oxide-based biosensor includes a nano-structure field-effect transistor including a channel region which includes a reduced graphene oxide having a linking moiety to be bonded to a receptor specific to an analyte, and which is represented by a formula of &#x2014;(C&#x2550;O)&#x2014;X&#x2014;COOH, wherein X represents a C1-C3 alkenylene group or a C1-C3 alkylene group.

Reduced graphene oxide-based biosensor and use thereof

A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.

Field-effect transistor structure having two-dimensional transition metal dichalcogenide

A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Thin film transistor and fabricating method

The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.

Nanowire fabrication method and semiconductor element using nanowire fabricated thereby

The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. The present disclosure uses a general method for mass-producing TFT and is thus fit for fabricating NAND-type or NOR-type flash memory to be used as embedded memory in a system-on-chip.

Method of manufacturing embedded metal-oxide-nitride-oxide-silicon memory device

Growing community of inventors

Hsinchu, Taiwan

Min-Cheng Chen