Texas Instruments Corporation

Min Chen

Vijay Kumar Reddy

John Michael Carulli, Jr

A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

Devices under test

An integrated circuit includes a circuit aging sensor that provides information regarding operational degradation of the integrated circuit due to aging. The aging sensor includes a ring oscillator that includes inverting drivers and tuning circuits. The drivers are sequentially coupled to form a ring. An output of each of the drivers is coupled to an input of one of the tuning circuits, and an input of each of the drivers is coupled to an output of one of the tuning circuits. Each of the tuning circuits includes a first signal path and a second signal path. The first signal path selectably applies a tuning delay to an input signal received from one of the drivers for provision to an input of a successive one of the drivers. The second signal path selectably routes the signal received around the tuning delay to the input of the successive one of the drivers.

Circuit aging sensor

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

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Allen, TX, United States of America

Min Chen