Skhynix Inc.

Min Chang Kim

Chang Hyun Kim

Jae Jin Lee

Do Yun Lee

Hun Sam Jung

Hyun Wook Han

Yong Woo Lee

Hoe Kwon Jung

Woo Yeol Shin

Noh Hyup Kwak

A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

Semiconductor circuit capable of swapping signal paths and semiconductor apparatus using the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.

Data I/O circuits and semiconductor systems including the same

A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal. The test data comparison circuit may generate a test result signal by comparing data output from the first data storage region, the second data storage region, the first data transfer circuit, and the second data transfer circuit and output the test result signal to the external equipment through the input/output pad.

Semiconductor device including chips capable of comparing data

A memory module may include a plurality of memory groups configured to include a plurality of memory packages, respectively, and input/output data through input/output pins. The memory module may include a control circuit configured to activate one or more of the plurality of memory groups on a basis of an address signal. The memory module may include a multiplexer circuit configured to couple the memory group activated on the basis of the address signal to input/output buses of the memory module.

Memory module including plurality of memory packages with reduced power consumption

A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive signals from the first chip to generate a latch address based on the received signals from the first chip.

Semiconductor device

A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.

Memory device and system including the same

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

Memory circuit and stack type memory system including the same

A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.

Semiconductor devices to store test data in memory cell array

A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

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Seoul, South Korea

Min Chang Kim