Samsung Electronics Co., Ltd.

Min Chan Gwak

Sang Hyun Lee

Young Woo Kim

Heon Jong Shin

Hwi Chan Jun

So Ra You

In Chan Hwang

Sung Moon Lee

Kyoung Woo Lee

Sung Hun Jung

Anthony Dongick Lee

Jeong Ki Hwang

Seul Ki Hong

Sang Cheol Na

Guk Hee Kim

A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

Method of manufacturing a semiconductor device having a node capping pattern and a gate capping pattern

Semiconductor device having a node capping pattern and a gate capping pattern

A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

Semiconductor devices including contact plugs

A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

Semiconductor device having a metal via

A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.

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Hwaseong-si, South Korea

Min Chan Gwak