Taiwan Semiconductor Manufacturing Comp. Ltd.

Min Cao

Chih-Hao Wang

Ching-Wei Tsai

Kuan-Lun Cheng

Chung-Te Lin

Chung-Cheng Wu

Sai-Hooi Yeong

Ta-Pen Guo

Sheng-Chih Lai

Hsiang-Jen Tseng

Shyue-Shyh Lin

Ali Keshavarzi

Zhiqiang Wu

Katherine H Chiang

Randy B Osborne

Shang-Wen Chang

Shau-Lin Shue

Li-Chun Tien

Lee-Chung Lu

Pei-Yu Wang

Tzer-Min Shen

Hsin-Ping Chen

Yung-Chin Hou

Sheng-Jier Yang

Jung-Chan Yang

Ru-Gun Liu

Kuo-Cheng Chiang

Yen-Ming Chen

Jiann-Tyng Tzeng

Li-Te S Lin

Ming-Han Lee

Chia-Tien Wu

Shin-Yi Yang

Ru-Shang Hsiao

Yu-Xuan Huang

Wei-Liang Lin

Han-Ting Tsai

David Barry Scott

Jung-Hung Chang

Yung-Hsu Wu

Pei-Hsun Wang

Ting Yu Chen

Yu-Hua Lee

Lo-Heng Chang

Tzong-Sheng Chang

Pin-Cheng Hsu

Yuh-Jier Mii

Chi-Hsing Hsu

Yen-Sen Wang

Chin-Yuan Tseng

Yen-Chung Ho

Shyh-Wei Wang

Ta-Ming Kuan

Chia-Hung Lai

Huan-Chi Tseng

Jiunn-Jyi Lin

Shu-Hui Sung

Chin-Tien Yang

Cheng-Tung Hsu

Chung Te Lin

Ka Hing Fung

Chi On Chui

Syun-Ming Jang Jang

Ziwei Fang

Ping-Wei Wang

Feng-Ming Chang

Jeff J Xu

Yimin Huang

Chang-Ta Yang

Kuan-lun Cheng

Ming-Jie Huang

Hsin-Yi Tsai

Wen-Kuo Hsieh

Jung-chan Yang

Ting-Yu Chen

Shu-Min Chen

Helen Shu-Hui Chang

Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Bipolar selector with independently tunable threshold voltages

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an operative memory device. A regulating access apparatus is coupled to the operative memory device. The regulating access apparatus includes one or more regulating MTJ devices respectively having a regulating free layer, a regulating dielectric barrier layer, and a regulating pinned layer separated from the regulating free layer by the regulating dielectric barrier layer. The regulating pinned layer continuously extends between opposing outermost sidewalls of the regulating dielectric barrier layer.

Transistorless memory cell

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Integrated circuit structure and method with hybrid orientation for FinFET

The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Metal oxide interlayer structure for NFET and PFET

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Semiconductor device structure and method for forming the same

The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dalong the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width Walong the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Dalong the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein D<D; each of the third and fourth ARs spans a second width Walong the direction; W<W; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Integrated hybrid standard cell structure with gate-all-around device

The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

Fully self-aligned interconnect structure

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Integrated circuits and manufacturing methods thereof

Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Barrier-less structures

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.

Semiconductor device with improved device performance

A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Negative capacitance transistor with external ferroelectric structure

Metal oxide interlayer structure for nFET and pFET

The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dalong the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width Walong the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Dalong the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein D&#x3c;D; each of the third and fourth ARs spans a second width Walong the direction; W&#x3c;W; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Growing community of inventors

Hsinchu, Taiwan

Min Cao