Samsung Electronics Co., Ltd.

Min-Bo Shin

Hitoshi Okamura

Sang-Jun Hwang

A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Clock and data recovery circuit having wide phase margin

A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Growing community of inventors

Suwon-si, South Korea

Min-Bo Shin