Cypress Semiconductor Corporation

Fyre Storm, Inc.

Exar Corporation

Parade Technologies, Ltd.

Ctpress Semiconductor Corporation

Fyresstorm, Inc.

Milton Ribeiro

Kent Kernahan

Andriy Maharyta

Oleksandr Karpin

Viktor Kremin

Roman Ogirko

Dongsheng Zhou

Igor Kolych

Oleksandr Hoshtanar

Jan-Willem Van De Waerdt

Volodymyr Bihday

Massoud Badaye

Ruslan Omelchuk

Peter G Vavaroutsos

Yuriy Boychuk

Bart Decanne

Mykhaylo Krekhovelskyy

A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of sensor electrodes corresponding to the unit cell than to a gap between any different pair of sensor electrodes, and a first trace pattern within a first unit cell of the plurality of unit cells may be different from a second trace pattern within an adjacent unit cell of the plurality of unit cells.

Sensor array with edge pattern

Apparatuses and methods of frequency hopping algorithms are described. One method monitors a signal on one or more electrodes of a sense network at a first operating frequency and detects noise in the signal at the first operating frequency. The method then switches to a second operating frequency, based on said detecting, for scanning the electrodes to detect a conductive object proximate to the plurality of electrodes, wherein a constant integration time is used for one half-period when scanning the electrodes at both the first and second operating frequencies.

Discontinuous integration using half periods

A processing device scans, during a first operation, a first plurality of electrodes along a first axis in a capacitive sense array to generate a first plurality of signals corresponding to a mutual capacitance at electrode intersections of the capacitive sense array. During a second operation, the processing device scans a second plurality of electrodes along a second axis in the capacitive sense array to generate a second plurality of signals corresponding to the mutual capacitance at the electrode intersections of the capacitive sense array, wherein the second operation occurs during a different period of time than the first operation. The processing device determines a first coordinate of a conductive object proximate to the capacitive sense array based on the first plurality of signals and a second coordinate of the conductive object based on the second plurality of signals.

Eliminating common mode noise in otuch applications

Apparatuses and methods of synchronizing a display driver integrated circuit (DDI) and a touch screen controller (TSC) integrated circuit that are coupled to a display integrated touch panel, such as an in-cell panel, and allowing multi-phase transmit (TX) scanning of the in-cell touch panel. One apparatus includes a DDI configured to receive signals on a video interface from a host processor over a video interface and to drive electrodes of a touch panel. The DDI is configured to receive control signals from a TSC over a control interface to drive different transmit (TX) phase sequences of a TX signal in different sensing interval on the electrodes of the touch panel.

Interface and synchronization method between touch controller and display driver for operation with touch integrated displays

A system comprises a processing device, a signal generator to generate a first signal and a single receiver to receive a second signal from a capacitive sense array. The single receiver is configured to process the second signal for stylus sensing of a stylus proximate to the capacitive sense array in a first mode of operation and to process the second signal for touch sensing of a passive touch object proximate to the capacitive sense array in a second mode of operation. The second signal is unsynchronized with the first signal.

Quadrature signal receiver using synchronized oscillator

A power converter circuit senses the output voltage (Vo) and controls the converter's duty cycle (d) to provide a steady output current (Io) or input power (Pin) in each switching cycle (T). During an initial period (Tramp), the controller provides a possibly smaller target current (Iramp) to reduce the system stress while the output voltage rises to a suitable value (InitVtar).

Output current and input power regulation with a power converter

To conserve power when regulating the output voltage (Vo) of a power converter, no adjustment is made to the converter's pulse width modulation times (Tp, Ts) even if the output voltage is off target (Vtar), provided that the output voltage does not change or is moving towards the target voltage. In some embodiments, the output voltage is not allowed to stay off target for more than a predetermined length of time. In some embodiments, the minimal adjustments are always large enough to overcome ringing ().

Power converters with limited operation to conserve power and with adjustments that overcome ringing

In a power converter, an input power source () is intermittently coupled to provide a current flow (Icoil) in consecutive cycles (T) to generate an output voltage (Vo). The coupling durations (Tp) are adjusted in conjunction with a cycle skip count (CNT) which is the count of cycles in which no coupling occurs. In some embodiments, the adjustments are performed to keep the coupling durations near the maximum efficiency range (between TLOW and THIGH), and the skip count is adjusted at the same time to obtain the desired output voltage in the presence of load current variations. The coupling frequencies are kept in a desired range to avoid interference with other circuit elements.

Power converters in which the input power coupling times are adjusted in conjunction with cycle skip counts

A method for controlling a switching power converter provides an efficient algorithm for controlling the output voltage across loads that are relatively light with small transients. When the output voltage is at or below a predetermined first magnitude, a determination is made of the charge required for one or more pulses to increase the output voltage to a predetermined second magnitude which is greater than a target output voltage. Corrective action is taken to raise the output voltage to the second magnitude and the system takes no further corrective action until output voltage is determined to be at or below the first magnitude. The method is useful with synchronous or non-synchronous power converters of buck, boost, buck/boost or other topologies. The method further provides a simple means for determining the amount of charge removed from a battery.

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Los Altos, CA, United States of America

Milton Ribeiro