International Telephone and Telegraph Corporation

Alcatel Network Systems, Inc.

Alcatel Na, Inc.,

Milton R Briscoe

Raymond E Tyrrell

Joseph E Sutherland

A transfer strobe delay stage selector insures accurate transfer of data from high speed circuitry to low speed circuitry through use of a delay stage module comprising a plurality of delay stages, and an associated multiplexor for selecting one of the delay stages so as to provide accurate reception of parallel data by the low speed circuitry from the high speed circuitry. The transfer strobe delay stage selector incorporates a synchronization channel identification module for detecting synchronization channel information in the frames of data transferred from the high speed circuitry to the low speed circuitry and also includes control circuitry for adjusting the selected delay stage until synchronization channel identification is detected. A second embodiment of the invention provides an auxiliary synchronization channel identification module and associated control circuitry to dynamically adjust the selected delay stage when variation in the propagation delay between the high speed and low speed circuitry occurs.

Transfer strobe time delay selector and method for performing same

A parallel time slot interchanger, particularly for use in telecommunication switching, comprises a plurality of switch groups, with each switch group containing a second plurality of channels. The parallel time slot interchanger incroporated a matrix-type architecture, with each module of the matrix comprising a switch block which in turn incorporates a switch memory, connect memory and associated control circuitry. The connect memory of each switch block is controlled by the control circuitry of that block. The data stored in the connect memory contains switch memory address information for reading channel data stored within the switch memory of the same switch block so as to be able to perform a time slot switching function during any given time slot of the parallel time slot interchanger. Each switch block is uniquely identified within its corresponding switch group so that only one switch memory address location is read and output during any time slot for each switch group.

Parallel time slot interchanger matrix and switch block module for use

A coding and decoding arrangement situated between and connected to digital and analog telecommunication lines includes a plurality of signal processing components which are arranged in respective receive and transmit paths and which process incoming digital signals and convert them into analog signals, and convert outgoing analog signals into digital signals and process the latter. A plurality of multiplexers is provided, each arranged ahead of one of the components in the respective receive and transmit path, and having respective test paths connected thereto. The multiplexers can be switched by control signals such as to selectively form test routes through the arrangement, each test route including a different combination of the components, so that testing signals can be sent through such components via the test routes for testing the performances of such components. An additional multiplexer is arranged at the ends of the test routes and is operative for selectively connecting such test routes to an output of the arrangement. The control signals are applied to control inputs of the multiplexers and selected combinations thereof are stored in respective memory locations of a test memory, to be called therefrom upon addressing of the respective memory location. The memory locations of the test memory are addressed by a test latch which is connected to a data bus carrying the respective address of the memory location to be addressed. The test latch is enabled by a signal issued by an externally controlled address decoder.

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Raleigh, NC, United States of America

Milton R Briscoe