Texas Instruments Corporation

Milton Lee Buschbom

Taylor R Efland

Sameer P Pendharkar

Anthony Louis Coyle

Samuel D Pritchett

Marco Corsi

Donald Charles Abbott

Louis N Hutter

Chi-Cheong Shen

John P Erdeljac

Charles E Williams

Konrad Wagensohner

Quang X Mai

Walter Bucksch

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m&#x3a9;/&#xb7; and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

Individualized low parasitic power distribution lines deposited over active integrated circuits

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m&#x3a9;/&#x25a1; and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.

Plastic chip-scale package having integrated passive components

A substrate ( ) for an unpackaged integrated circuit (IC) chip ( ). The substrate comprises an insulative material ( ), a plurality of contacts ( ) disposed thereon, and a conductive ring ( ) disposed around the outer perimeter of the contacts ( ). Conductive traces ( ) may be disposed around one or more contacts ( ) and may be coupled to the conductive ring ( ). An electro-less plating technique is utilized to plate contacts ( ), avoiding unnecessary conductive material such as plating stubs being included in the contact ( ) pattern, reducing interference. The conductive ring ( ) shields the chip ( ) from interference.

Power/ground ring substrate for integrated circuits

An integrated circuit device ( ) with a bonding surface ( ) directly over its active circuitry, and a method of making such integrated circuits (FIGS. A- E). To make the bonding surface ( ), a wafer ( ) is provided with vias ( ) to its metallization layer ( ) and then coated with a seed metal layer ( ). A plating pattern ( ) is formed on the wafer ( ), exposing portions of the seed metal layer ( ) and blocking the rest of the seed metal layer ( ). These exposed portions are plated with successive metal layers ( ), thereby forming a bonding surface ( ) having a number of layered stacks ( ) that fill the vias ( ). The plating pattern and the nonplated portions of the seed metal layer ( ) are then removed.

Integrated circuit with bonding layer over active circuitry

A method and apparatus are provided for integrated circuit testing applications. One aspect of the invention is a contactor (10) for test applications. The contactor (10) comprises a membrane carrier (12) having at least one contact (16) on the surface of the carrier (12) electrically connected to at least one terminal (18) on the carrier (12). A pin (14) is metallically bonded to the terminal (18).

Contactor for test applications including membrane carrier having

The invention is to a combination of a semiconductor device and a ground plane on a printed wiring board to provide a controlled impedance signal lead. A printed wiring board has a ground plane layer, and a semiconductor device having a down-set, or deep down-set, lead frame die mounting pad is mounted on the printed wiring board above the ground plane layer. The leads of the semiconductor device form a transmission line in combination with the ground plane, when the leads are placed a controlled distance above the ground plane.

Printed circuit board ground plane and high frequency semiconductor

A method is disclosed for making a non-metallurgical connection between an integrated circuit (16) and either a circuit board (12) or second integrated circuit. In one embodiment, an electrical connection is formed between terminals (28) of an integrated circuit (16) and pads (20) on a circuit board (12) without metallurgically connecting the terminals (28) and pads (20). The integrated circuit (16) can be in either packaged or die form. A clamping mechanism (18, 36) attached to the circuit board (12) clamps the integrated circuit (16) to the circuit board (12).

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Plano, TX, United States of America

Milton Lee Buschbom