International Business Machines Corporation

Milos Stanisavljevic

Nikolaos Papandreou

Charalampos Pozidis

Thomas Mittelholzer

Abu Sebastian

Thomas P Parnell

Manuel Le Gallo-Bourdeau

Tobias Blaettler

Geoffrey W Burr

Andreea Anghel

Shubham Jain

Riduan Khaddam-Aljameh

Evangelos Stavros Eleftheriou

Daniel Frank Moertl

Charles John Camp

Robert Edward Galbraith

Angeliki Pantazi

Jan Van Lunteren

Damir Anthony Jamsek

Yasuteru Kohda

Andrew Kenneth Martin

Lukas Kull

Tomas Tuma

Pritish Narayanan

HsinYu Tsai

Martin Petermann

Robert Allan Cyprus

Mussie T Negussie

Sonali Andani

Vinay Manikrao Joshi

A method of dynamically optimizing decision tree inference is provided. The method, which is performed at the computerized system, repeatedly executes one or more decision trees for inference purposes and repeatedly performs an optimization procedure according to two-phase cycles. Each cycle includes two alternating phases, i.e., a first phase followed by a second phase. The decision trees are executed based on a reference data structure, whereby attributes of nodes of the decision trees are repeatedly accessed from the reference data structure during the first phase of each of the cycles. First, the accessed attributes are monitored during the first phase of each cycle, which leads to update statistical characteristics of the nodes. Second, a substitute data structure is configured during the second phase of each cycle based on the updated statistical characteristics. Third, the reference data structure is updated in accordance with the substitute data structure.

Dynamically optimizing decision tree inferences

Embodiments disclosed herein include a compute in-memory (CIM) accelerator architecture for deep neural network (DNN). The CIM accelerator architecture may include a first analog fabric engine having a plurality of compute in-memory (CIM) analog tiles. Each CIM analog tile may be configured to store a matrix of weight operands producing a vector of outputs from a vector of inputs, and perform in-memory computations. The first analog fabric may also include a plurality of compute cores. Each CIM analog tile and each compute core may include a microcontroller configured to execute a set of instructions. The first analog fabric may also include on-chip interconnects communicatively connecting all CIM analog tiles in the plurality of CIM analog tile to the compute cores.

Two-dimensional mesh for compute-in-memory accelerator architecture

The exemplary embodiments disclose a method, a computer program product, and a computer system for a gated recurrent neural network (RNN). The exemplary embodiments may include providing an element processor, providing a distinct memory array for a respective set of one or more elements of a hidden state vector, storing in the memory array a group of columns of weight matrices that enable a computation of the set of one or more elements, computing one or more elements of each of multiple activation vectors using a set of one or more columns of the group of columns associated with each of the multiple activation vectors, and performing by the element processor an elementwise gating operation on computed elements, resulting in the set of one or more elements.

Gated unit for a gated recurrent neural network

An efficient pipelined implementation of digital scaling, offset and aggregation operation supports element-by-element programmable scale and offset factors. The method includes time-multiplexed parallel pipelining of a plurality of digital data words, each of the plurality of digital data words encoding an N-bit signed integer, from one of a plurality of receive-registers through a datapath that can either (1) store the plurality of digital data words directly in a dedicated first memory, (2) store the plurality of digital data words directly in a dedicated second memory, or (3) direct the plurality of digital data words into a parallel set of fused-multiply-add units. The method further includes multiplying each digital data word by a corresponding data-word retrieved from the dedicated first memory to form product data words and adding the product data words to a corresponding data-word retrieved from the dedicated second memory to form an output sum-and-product data words.

Special-purpose digital-compute hardware for efficient element-wise aggregation, scaling and offset

The invention is notably directed to a computer-implemented method for normalizing medical images, e.g., whole slide images. This method includes steps performed for each image of a first subset of images of a dataset. Actual quantities are estimated for each image, including actual stain vectors and, possibly, robust maximum stain concentrations (typically hematoxylin and eosin stain vectors and concentrations). The actual quantities estimated are assessed by comparing them to reference data based on reference quantities estimated for one or more images of a second subset of images of the dataset, where the second subset of images differ from the first subset of images. The reference quantities include reference stain vectors. For each image, either the actual quantities or the reference quantities for the dataset are selected as effective quantities, based on an outcome of the previous assessment of the actual quantities. Each image is then normalized.

Pre-processing whole slide images in cognitive medical pipelines

Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.

Dynamic mapping of logical to physical memory for increased performance

Processing a digital image in a distributed computing environment comprising a communications network interconnecting two or more computing nodes. A segmentation of the digital image into two or more image segments is determined. For each of the image segments, a number of non-background pixels comprised by the image segment is determined. An assignment of each of the image segments to one of the computing nodes is determined. The determination of the assignment may include balancing, based on the number of non-background pixels determined for each of the image segments, the workload of the assigned computing nodes responsive to processing the image segments. Each of the assigned computing nodes may be caused to process the image segments assigned to the computing node.

Distributed processing of a digital image

A memory system, Reed Solomon ('RS') Decoder, and method for decoding Reed-Solomon codewords includes: a Syndrome Computation engine configured as a first stage of a pipeline for receiving the RS codeword and computing one or more Syndromes; an initialization unit for providing initialization values for a key equation solver engine that generates the errata locator polynomial and the errata magnitude polynomial configured as a second stage; and as a third stage a Chien Search engine for receiving the error locator polynomial and determining the one or more locations of the one or more erasures and random errors in the received RS codeword and an error-value evaluation ('EE') engine for receiving the errata magnitude polynomial and determining the one or more magnitudes of the one or more erasures and random errors in the RS received codeword.

System and method for optimizing Reed-Solomon decoder for errors and erasures

A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.

Virtual to physical translation and media repair in storage class memory

A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

Resistive memory device for matrix-vector multiplications

A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.

Efficient error correction of codewords encoded by binary symmetry-invariant product codes

A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.

Resistive memory device with scalable resistance to store weights

A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages.

Method and apparatus for determining a cell state of a resistive memory cell

Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.

Artificial neuron apparatus

Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q&#x2212;1 elements corresponding, respectively, to q&#x2212;1 level-thresholds which partition the signal level vector into q segments, is then defined. The q&#x2212;1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

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Adliswil, Switzerland

Milos Stanisavljevic