Intel Corporation

Milo David Sprague

Robert J Murray

The pulsed reset single phase dynamic logic of the present invention reorders the conventional modes of operation such that in a single cycle of operation of a domino logic circuit, reset occurs first, followed sequentially by gap2, evaluation and gap1. To reset each domino stage prior to evaluating, a reset pulse is propagated to each domino stage, with an evaluate signal arriving at each stage as the reset pulse is ending. The circuit configuration of the present invention creates a different, but shorter and easier to manage set of race conditions. The present invention permits the creation of faster and more robust circuit designs.

Pulsed reset single phase domino logic

The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.

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Aloha, OR, United States of America

Milo David Sprague