Qualcomm Incorporated

Rf Micro Devices, Inc.

Milind Shah

Jonghae Kim

Periannan Chidambaram

Chin-Kwan Kim

Omar James Bchir

Thomas Scott Morris

Rajneesh Kumar

Manuel Aldrete

Brian D Sawyer

Jon D Jorgenson

Donald Joseph Leahy

Jie Fu

Mario Francisco Velez

Michael R Kay

Je-Hsiung Lan

David C Dening

Houssam Jomaa

Ryan David Lane

Jaehyun Yeon

Suhyung Hwang

David Fraser Rae

Ulrik Riis Madsen

Ahmer Raza Syed

Fifin Sweeney

Abdolreza Langari

Vladimir Noveski

Sashidhar Movva

T Scott Morris

Steve Dorn

Yang Rao

Xia Li

Evgeni Petrovich Gousev

David Jon Hiner

Matthew Michael Nowak

Hong Bok We

Gurkanwal Singh Sahota

Ravindra Vaman Shenoy

Aristotele Hadjichristos

Ranadeep Dutta

Kuiwon Kang

Steven C Ciccarelli

Chi Shun Lo

Christian Holenstein

Jayanti Jaganatha Rao

David Halchin

David Jandzinski

John Robert Siomkos

Damion B Gastelum

Marcus Hsu

Dan Carey

Mohsen Haji-Rahim

Waite R Warren, Jr

Brian Howard Calhoun

Mark Charles Held

Dwayne Richard Shirley

Mark Alan Crandall

Carl Hinshaw

David J Wilding

Lewis Kermit Law, Ii

Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

Integrated circuit assembly with hybrid bonding

A reconstituted substrate, a packaged assembly comprising a reconstituted substrate, and methods for fabricating a reconstituted substrate. An example reconstituted substrate generally includes multiple package-level substrates implemented with different substrate technologies and held together. An example method for fabricating a reconstituted substrate generally includes forming multiple package-level substrates implemented with different substrate technologies, arranging the multiple package-level substrates, and adding a material to hold the multiple package-level substrates together.

Hybrid reconstituted substrate for electronic packaging

Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.

Trench capacitor assembly for high capacitance density

A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

Substrate comprising an inductor and a capacitor located in an encapsulation layer

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

Package with a substrate comprising protruding pad interconnects

An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.

Sub-module L-shaped millimeter wave antenna-in-package

A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

Package comprising stacked filters with a shared substrate cap

Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.

Stacked decoupling capacitors with integration in a substrate

Reducing the space occupied by a voltage regulation integrated circuit (IC) that includes an inductor is achieved by implementing the inductor as a 3D inductor having windings formed of conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with the other circuit components and with the structural layers of the voltage regulation IC. A voltage regulation IC may be a switched-mode power supply (SMPS) that includes an inductor with a capacitor and/or a switching circuit. The inductor is implemented as upper horizontal traces in an upper substrate, lower horizontal traces in a lower substrate, and vertical interconnects in a circuit layer between the upper substrate and the lower substrate, and the conductive elements form the 3D inductor as a rectangular coil.

Voltage regulation integrated circuit (IC) with circuit components in an integrated three-dimensional (3D) inductor core and related methods of fabrication

Impedance matching transceivers may include a tuning circuit to match the transceiver module impedance to the housing conditions. In some examples, the impedance matching is controlled by tuning-circuits that may be integrated into a transceiver module by using a fan-out package (FO PKG). One example of a tuning circuit may include a switch to isolate the parallel capacitors, such that when the switch is on or closed the parallel capacitors are active.

Impedance matching transceiver

An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.

A device that includes a first package and a second package coupled to the first package. The first package includes a first integrated device, a first encapsulation layer encapsulating the first integrated device, a plurality of vias traveling through the first encapsulation layer, a first redistribution portion comprising a first plurality of redistribution interconnects, wherein the first redistribution portion is coupled to the first encapsulation layer, and a first plurality of contacts coupled to the first integrated device. The second package includes a passive device, a second encapsulation layer encapsulating the passive device, a second redistribution portion comprising a second plurality of redistribution interconnects, wherein the second redistribution portion is coupled to the passive device and the second encapsulation layer, and a second plurality of contacts coupled to the passive device, wherein the second plurality of contacts is coupled to the first plurality of contacts from the first package.

Device comprising contact to contact coupling of packages

A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.

Integrated device coupled to a capacitor structure comprising a trench capacitor

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San Diego, CA, United States of America

Milind Shah