Hewlett Packard Enterprise Development LP

Hewlett Packard Enterprise Patent Development LP

Milind M Chabbi

Hideaki Kimura

Haris Volos

Tianzheng Wang

Michael S Schlansker

Harumi Kuno

Mark David Lillibridge

Kimberly Keeton

Charles Stuart Johnson

Joseph Andrew Tucek

Yupu Zhang

Mesut Kuscu

Onkar Patil

Tuan Tran

Adarsh Yoga

William Scherer

In example implementations, a method include receiving a request for a lock in a Mellor-Crummey Scott (MCS) lock protocol from a guest user that is context free (e.g., a process that does not bring a queue node). The lock determines that it contains a null value. The lock is granted to the guest user. A pi value is received from the guest user to store in the lock. The pi value notifies subsequent users that the guest user has the lock.

Request of an MCS lock by guests

Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.

Concurrent reading and writing with crash recovery in persistent memory

Examples disclosed herein relate to path-synchronous performance monitoring of an interconnection network based on source code attribution. A processing node in the interconnection network has a profiler module to select a network transaction to be monitored, determine a source code attribution associated with the network transaction to be monitored, and issue a network command to execute the network transaction to be monitored. A logger module creates, in a buffer, a node temporal log associated with the network transaction and the network command. A drainer module periodically captures the node temporal log. The processing node has a network interface controller to receive the network command and mark a packet generated for the network command to be temporally tracked and attributed back to the source code attribution at each hop of the interconnection network traversed by the marked packet.

Path-synchronous performance monitoring of interconnection networks based on source code attribution

A high performance computing system including processing circuitry and a shared fabric memory is disclosed. The processing circuitry includes processors coupled to local storages. The shared fabric memory includes memory devices and is coupled to the processing circuitry. The shared fabric memory executes a first sweep of a stencil code by sequentially retrieving data stripes. Further, for each retrieved data stripe, a set of values of the retrieved data stripe are updated substantially simultaneously. For each retrieved data stripe, the updated set of values are stored in a free memory gap adjacent to the retrieved data stripe. For each retrieved data stripe, the free memory gap is advanced to an adjacent memory location. A sweep status indicator is incremented from the first sweep to a second sweep.

Sequential memory access on a high performance computing system

In one example in accordance with the present disclosure, a method may include performing a transactional operation such that if one step of the transactional operation is performed, each other step of the transactional operation is performed. The transactional operation may include making a first copy, stored in a first persistent memory, of a next ticket number stored in a second persistent memory and updating the next ticket number in the second persistent memory. The method may also include determining when to serve a first thread based on the first copy of the next ticket number.

Persistent ticket operation

Growing community of inventors

Palo Alto, CA, United States of America

Milind M Chabbi