Vlsi Technology, Inc.

Intermolecular, Inc.

Koninklijke Philips Corporation N.v.

Cadence Design Systems, Inc.

Philips Electronics North America Corporation

Kabushiki Kaisha Toshiba

Sandisk 3d LLC

Vsli Technology, Inc.

Milind Ganesh Weling

Calvin T Gabriel

Subhas Bothra

Charles Franklin Drill

Dipankar Pramanik

Abdurrahman Sezginer

Rao Venkateswara Annapragada

Vivek Jain

Judy Huckabay

Michael N Misheloff

Tony P Chiang

Yun Yu Wang

Federico Nardi

Samuel Vance Dunton

Daniel C Baker

Liming Zhang

Xi-Wei Lin

Minh Le

Vidyut Gopal

Ian Robert Harvey

Mihir Tendulkar

Minh Anh Nguyen

Satyendra S Sethi

Hunter B Brugge

Ramiro Solis

David Chi

David E Henderson

Olivier F Laparra

Richard D Russ

Bijan Moslehi

Michela S Love

A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (&#x394;fG&#xb0;) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiOinterfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Nonvolatile resistive memory element with an oxygen-gettering layer

Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode.

Stacked bi-layer as the low power switchable RRAM

Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state. The embedded resistor includes a stoichiometric nitride that has a bandgap of less than 2 eV. The embedded resistor is configured to maintain a substantially constant resistance throughout fabrication and operation of the cell, such as annealing the cell and subjecting the cell to forming and switching signals. The stoichiometric nitride may be one of hafnium nitride, zirconium nitride, or titanium nitride. The embedded resistor may also include a dopant, such as tantalum, niobium, vanadium, tungsten, molybdenum, or chromium.

Doped narrow band gap nitrides for embedded resistors of resistive random access memory cells

A resistive-switching memory (ReRAM cell) has a current-limiting electrode layer that combines the functions of an embedded resistor, an outer electrode, and an intermediate electrode, reducing the thickness of the ReRAM stack and simplifying the fabrication process. The materials include compound nitrides of a transition metal and one of aluminum, boron, or silicon. In experiments with tantalum silicon nitride, peak yield in the desired resistivity range corresponded to24 at % silicon and32 at % nitrogen, believed to optimize the trade-off between inhibiting TaSiformation and minimizing nitrogen diffusion. A binary metal nitride may be formed at one or more of the interfaces between the current-limiting electrode and neighboring layers such as metal-oxide switching layers.

Current-limiting electrodes

Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.

Resistive random access memory cells having doped current limiting layers

Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

Method of eliminating a lithography operation

Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Method for self-aligned doubled patterning lithography

Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer.

The present invention comprises a customized polishing pad for use in a wafer polishing machine. The polishing pad of the present invention includes a polishing surface integral with the polishing pad. The polishing surface is adapted to frictionally contact a wafer in the polishing machine, thereby polishing the wafer. The polishing surface of the polishing pad includes at least two areas, where each area is adapted to frictionally contact the wafer and achieve a polishing effect specific for that area. A customized polishing effect is achieved by the polishing pad of the present invention when the wafer is selectively moved frictionally against the at least two areas by the wafer polishing machine.

Customized polishing pad for selective process performance during chemical mechanical polishing

A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection

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San Jose, CA, United States of America

Milind Ganesh Weling