Intel Corporation

Intel Corporatoin

Milind Baburao Girkar

Robert Valentine

Elmoustapha Ould-Ahmed-Vall

Mark Jay Charney

Jesus Corbal

Bret L Toll

Christopher J Hughes

Xinmin Tian

Zeev Sperber

Hong Wang

Simon Rubanovich

Edward Thomas Grochowski

Perry H Wang

Amit Gradstein

Dennis Ryan Bradford

Jonathan Cannon Hall

Jesus Corbal San Adrian

Jeffrey G Wiedemeier

Alexander F Heinecke

Dan Baum

Barukh Ziv

John P Shen

Galina Ryvchin

Jason W Brandt

Per H Hammarlund

John Thomas Shen

Menachem Adelman

Andrew Thomas Forsyth

Robert Dale Cavin

Stanislav Shwartsman

Xiang Chris Zou

Igor Yanover

Suleyman Sair

Seth Abraham

Charles R Yount

Rinat Rappoport

Sridhar Samudrala

Yuri Gebil

James Charles Abel

Piyush N Desai

Thomas D Fletcher

Wei Ey Li

Chris J Newburn

Gerolf F Hoflehner

Hideki Ido

Gilbert A Neiger

Martin Guy Dixon

Avinash Sodani

Srinivas Chennupaty

Rajesh S Parthasarathy

Richard J Greco

Mark J Buxton

Andreas Kleen

Peter Lachner

Daniel M Lavery

Mayank Bomb

Baiju V Patel

Raanan Sade

Michael Lemay

Sara S Baghsorkhi

Prashant Sethi

Gautham N Chinya

Venkateswara Rao Madduri

Victor W Lee

Shivnandan D Kaushik

Bryant E Bigbee

Deborah T Marr

Richard A Hankins

Daehyun Kim

Asit K Mallick

James Paul Held

Ehud Cohen

Cristina S Anderson

Jonathan D Pearce

Trung Am Diep

Asit K Mishra

Robert Geva

Mohammad R Haghighat

Jayashankar Bharadwaj

Albert Hartono

Sanjiv M Shah

Nalini Vasudevan

Marius A Cornea-Hasegan

Carl Murray

Cheng C Wang

Youfeng Wu

Bratin Saha

Yen-Kuang Chen

Mikhail Plotnikov

David Sehr

Stephen Junkins

David M Putzolu

Ying Gao

Shoumeng Yan

Mohan Rajagopalan

Aart J C Bik

Roger Espasa

Xiaocheng Zhou

Sai Luo

Roni Rosner

Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

Systems, methods, and apparatuses for matrix add, subtract, and multiply

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.

Systems, apparatuses, and methods for addition of partial products

Embodiments detailed herein relate to matrix operations. In particular, support for a matrix transpose instruction is detailed. In some embodiments, decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand are detailed.

Systems, methods, and apparatuses for tile transpose

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

Systems, apparatuses, and methods for chained fused multiply add

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.

Systems, methods, and apparatuses for tile store

A processor core that includes a token generator circuit is to execute a first instruction in response to initialization of a software program that requests access to protected data output by a cryptographic operation. To execute the first instruction, the processor core is to: retrieve a key that is to be used by the cryptographic operation; trigger the token generator circuit to generate an authorization token; cryptographically encode the key and the authorization token within a key handle; store the key handle in memory; and embed the authorization token within a cryptographic instruction that is to perform the cryptographic operation. The cryptographic instruction may be associated with a first logical compartment of the software program that is authorized access to the protected data.

Protection of keys and sensitive data from attack within microprocessor architecture

Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Systems, apparatuses, and methods for controllable sine and/or cosine operations

Systems, methods, and apparatuses for tile load

Systems, apparatuses, and methods for fused multiply add

In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

Providing multiple memory modes for a processor including internal memory

Growing community of inventors

Sunnyvale, CA, United States of America

Milind Baburao Girkar