Intel Corporation

Milind A Bodas

Glenn J Hinton

Andrew F Glew

Lavi A Lev

Nagaraj Palasamudram

A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine whether the entry corresponds to the first memory location. The entry is also tested to determine whether the entry corresponds to a second memory location subsequent to the first memory location. The load request is blocked if the entry corresponds to the first memory location or the second memory location. After a store operation for the store buffer entry is executed, the load request may be unblocked. The apparatus is a processor or a computer system comprising a load buffer capable of storing a load request address in response to a load request. The processor includes an incrementing circuit that generates an incremented load request address. The processor also includes a store buffer containing a portion of a store request address. The store buffer includes comparison circuitry that compares the portion of the store request address to the load request and the incremented load request address, and generates a blocking signal if the either of the load request address and the incremented load request correspond to the store request address.

Mechanism to improved execution of misaligned loads

A noise suppression circuit for a floating bus in a digital integrated circuit includes pull-up and pull-down feedback loops each connected to the floating bus. The pull-up feedback loop includes a PMOS device connected between a high logic level and the floating bus, with a NOR gate switching the PMOS device. The pull-down feedback loop includes an NMOS device connected between a low logic level and the floating bus, with a NAND gate switches the NMOS device. The NOR and NAND gates are configured such that one of their inputs is connected directly to the floating bus and the other input is connected to the floating bus through an inverter having a finite gate delay. Voltage transitions occurring on the floating bus due to noise injection drive the bus back to its original state before the finite gate delay of the inverter.

Noise suppressing circuit for VLSI

XOR and XNOR logic gates each include a first MOS pass device coupled between a first input and the output of the logic gate, and second MOS pass device coupled between a second input and the output of the logic gate. The control input of the first pass device is coupled to the second input and the control input of the second pass device is coupled to the first input. First and second logic signals are coupled to first and second inputs, respectively. First and second input signals are also coupled to third and fourth MOS devices, respectively. Third and fourth MOS devices are coupled in series between the logic gates output and a reference potential. The first and second MOS pass devices have the opposite channel type than the third and fourth MOS devices such that the XOR gate includes first and second PMOS pass gates and third and fourth NMOS devices. The XNOR gate includes first and second NMOS pass gates and third and fourth PMOS devices.

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Sunnyvale, CA, United States of America

Milind A Bodas