International Business Machines Corporation

Miles G Canada

Jay Gerald Heaslip

Mathew I Ringler

Cedric Lichtenau

Thomas Pflueger

Gerard M Salem

Robert Maurice Houle

Vinod Ramadurai

Stephen Frank Geissler

Stephen William Mahin

James Henry Hesson

Erwin B Cohen

John R Rawlins

Timothy J Vonreyn

Carlos G Rivadeneira

Dongho Lee

Michael Nicewicz

Walter Esling

Pamela A Wilcox

A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.

Clock dithering system and method during frequency scaling

A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.

Method and circuit for dynamic read margin control of a memory array

An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set. The second instruction is subsequent in the succession to the first instruction. The first register storage set is a first storage locus for storing a target operand of the first instruction; the second register storage set is a second storage locus for storing a source operand for the second instruction. The logical treating effects the identifying of dependencies between the target operand and the source operand.

Method and apparatus for identifying dependencies within a register

In a method and apparatus for result forwarding, a source operand compare circuit for a reservation station for a superscalar processor having a plurality of execution units, includes a source identifier for identifying an execution unit that will produce a needed result. The source identifier is included with a rename tag associated with a respective source operand. A multiplexor controlled by the source identifier directs the result of an execution unit to a comparator. The comparator compares the rename tag with a specific reservation station identity. As a result of this comparison, the needed data result is supplied to the respective source operand.

Source identifier for result forwarding

A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse latch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.

Fuse blow circuit

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Colchester, VT, United States of America

Miles G Canada