The Plessey Company Plc

Milan Z Maric

Geoffrey Chopping

Ian J Lawrie

The synchronization arrangement includes a waveform and synchronization information generator to supply synchronization information for transmission with a data stream over digital switching networks. The synchronization information includes two different patterns, phased displaced with respect to each other. Interfaces connect peripheral devices to the networks and are adapted to detect a validate the synchronization information. The checks made are in respect of detecting both patterns, the amount of phase displacement, and the correct sequence. If the synchronization information is invalid, the detecting interface selects a data stream from another network exclusively for use by the corresponding peripheral device.

Synchronization arrangements for a digital telecommunications exchange

An aligner (FIG. 1), which has seven registers SRGA to SRGG each of 64 bits in length, is used to align incoming line signals to exchange data rate and to convert exchange rate data signals into line rate data signals. The aligner behaves as a variable delay and is required to operate in any one of three modes; (i) frame aligning 2,048 k Bits/second line signals to a 2,048 k Bits/second exchange rate, (ii) aligning 1,544 k Bits/second line signal to a 2,048 k Bits/second exchange rate and (iii) converting a 2,048 k Bits/second exchange rate to a 1,544 k Bits/second line rate. In the third mode of operation it is necessary to derive the line clock from the exchange local clock. This is achieved by forming a phase-locked loop (FIG. 5) incorporating the delay of a standard aligner and driving the loop with the exchange frame reset signal (f IN).

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Wimborne, United Kingdom

Milan Z Maric