Emc Corporation

Miklos A Sandorfi

Kendell Alan Chilton

Brian K Campbell

Brian William Gallagher

Man Min Moy (Joshua)

Man Min (Joshua) Moy

Moshe M Shriki

A central processing unit having: (A) a microprocessor; (B) a main memory; (C) a microprocessor interface. The interface includes: a semiconductor integrated circuit having formed therein: (i) a data rebuffering section disposed in the chip and adapted to couple data from a one of a plurality of data ports to a data port of the microprocessor selectively in accordance with a control signal; and (ii) a main memory interface adapted for coupling to a main memory for the microprocessor, such main memory interface being adapted for coupling to the microprocessor and being coupled to the data rebuffering section for providing control signals to the main memory section for enabling data transfer between the main memory and the microprocessor through the data rebuffering section.

Central processing unit

A microprocessor interface having: (i) a data rebuffering section to couple data from a one of a plurality of data ports to a data port of the microprocessor selectively in accordance with a control signal; and (ii) a main memory interface for coupling to a main memory for the microprocessor, such main memory interface being coupled to the data rebuffering section for providing control signals to the main memory section for enabling data transfer between the main memory and the microprocessor through the data rebuffering section. The main memory is a selected one of a plurality of memory types each type having a different data transfer protocol and the main memory interface is configured in accordance with the selected one of the plurality of memory types to provide a proper memory protocol to data being transferred between the microprocessor and the main memory through the main memory interface.

Microprocessor interface

A central processing unit having: (A) a microprocessor; (B) a main memory; (C) a microprocessor interface. The interface includes: a semiconductor integrated circuit having formed therein: (i) a data rebuffering section disposed in the chip and adapted to couple data from a one of a plurality of data ports to a data port of the microprocessor selectively in accordance with a control signal; and (ii) a main memory interface adapted for coupling to a main memory for the microprocessor, such main memory interface being adapted for coupling to the microprocessor and being coupled to the data rebuffering section for providing control signals to the main memory section for enabling data transfer between the main memory and the microprocessor through the data rebuffering section. A controller is coupled to the data rebuffering section for producing the control signal. The main memory is a selected one of a plurality of memory types each type having a different data transfer protocol and the main memory interface is configured in accordance with the selected one of the plurality of memory types to provide a proper memory protocol to data being transferred between the microprocessor and the main memory through the main memory interface. One main memory type is an SDRAM or a RDRAM.

A data storage system wherein a host computer is in communication with a bank of disk drives through an interface. The interface includes: a memory; a plurality of directors for controlling data transfer between the host computer and the bank of disk drives as such data passes through the memory; and a plurality of busses in communication with the directors and the memory. Each one of the directors includes a central processing unit. The central processing unit includes: (A) a microprocessor; (B) a main memory; and (C) a microprocessor interface. The microprocessor interface includes: (i) a data rebuffering section disposed in the chip and adapted to couple data from a one of a plurality of data ports to a data port of the microprocessor selectively in accordance with a control signal; and (ii) a main memory interface adapted for coupling to a main memory for the microprocessor, such main memory interface being adapted for coupling to the microprocessor and being coupled to the data rebuffering section for providing control signals to the main memory section for enabling data transfer between the main memory and the microprocessor through the data rebuffering section. A controller is coupled to the data rebuffering section for producing the control signal. The central processing unit main memory is a selected one of a plurality of memory types each type having a different data transfer protocol and the main memory interface is configured in accordance with the selected one of the plurality of memory types to provide a proper memory protocol to data being transferred between the microprocessor and the main memory through the main memory interface. One main memory is an SDRAM and another a RDRAM.

Data storage system

A method and apparatus for checking errors in data. The method includes transmitting data along with parity bits to a first end of a data transmission network; generating check bits from the data as such data passes through the network; comparing the check bits with the parity bits to determine whether there has been an error generated by the network. The error detector apparatus includes: a data source for providing data. The data has a plurality of bytes, each byte having a parity bit. A first logic is provided for determining whether the parity bits have the same parity and for producing a combined parity bit representative of such determination. A check bit generator produces a plurality of check bits from the data. A second logic determines whether the produced check bits have the same logic state and produces a combined check bit representative of such determination. A third logic determines whether the combined check bit and the combined parity bit have the same logic state. The check bit generator produces the check bits in accordance with a redundancy check bit generating code, for example a modified Hamming code.

Error corrector

A circuit for detecting a fault on a bi-directional data line. The circuit includes: an input/output terminal connected to one end of the bi-directional line; a data receiver having an input coupled to a second end of the bi-directional line for receiving data on the terminal; a data driver having an output coupled to the second end of the bi-directional line for producing data on the terminal; an XOR gate having a pair of inputs, one being coupled to an output of the data receiver and the other being coupled to an input of the data driver, for determining whether data produced by the data driver is received by the data receiver.

Fault detector

A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

Data transfer state machines

Data transfer apparatus having upper, lower, middle state machines, with middle state machine arbitrating among lower state machine side requesters including selective assembly/disassembly requests

A method and apparatus for communicating multiple threads, concurrently on a single channel, features a process for prioritizing and limiting the transmission time allocated to any particular host. The invention features providing a channel switch capable of communicating with a plurality of client sources, the sources being connected for transmitting frames of data to the channel, and to at least one storage device connected to the channel. The information transmission is formatted and controlled at the switch in accordance with a frame protocol and the protocol provides a predetermined method for selecting which information host to connect to which channel and for how long. The switch allocates connection line capacity to the sources according to a selected priority and the credit or buffer available to the source. Accordingly, an average priority waiting is associated with each information source.

Method and apparatus for controlling concurrent data transmission from

An application specific circuit for acting as an interface between a data processing system and a high speed data channel. A single integrated circuit includes an interface circuit for transferring data to and from a high speed data channel such as a fibre channel that transfers information in frames according to specific protocols. A frame processing circuit receives and transmits data frames according to the protocol and processes incoming data frames to facilitate subsequent handling. A sequence management circuit transfers data frames to and from a local memory system. When data frames are received out of order, the sequence management circuit provides a mechanism for establishing the appropriate order. The sequence management circuitry initially includes circuitry for transferring data between the local memory system and a data processing system. Both the local memory system and the data processing system are external to the application specific integrated circuit.

High speed integrated circuit interface for fibre channel communications

The invention relates to a method and apparatus for checking data integrity in a data communications system in which plural data streams can be intermixed and wherein the data streams have a frame transmission format in which the frame is different than the logical block length of the data stream components. The integrity of the transmission process is checked without requiring system processor involvement, unless errors are detected. A first incoming data stream, composed of logical blocks, is received; and a running longitudinal redundancy check is calculated. If the data stream is interrupted at other than the end of a block, the intermediate value of the LRC is stored in a context storage associated only with that data stream. When the data stream continues, and this may occur after other data streams have been received, the intermediate value of the LRC is recalled from the context storage and the running longitudinal redundancy check calculation is continued. The storage and calculation steps continue each time the data stream is interrupted other than at a logical termination of a logical block for the data stream. The communications process is particularly applicable to mass storage subsystems in which the data streams are directed to and from the storage media.

Method and apparatus for calculating the longitudinal redundancy check

A buffer having a predetermined number, M, of input ports adapted for connection to one of a plurality of devices. The devices have different numbers, P, of ports, where P is less than, or equal to, M. The buffer includes a processor for determining the number of ports, P, of the one of the plurality of devices connected to the M ports of the buffer. The buffer couples the P ports of the device to M output ports of the buffer in a ratio of [M/P] sequences. A method for determining the number, P, of transmit/receive ports of one of a plurality of devices. After connecting one of the plurality of devices to the buffer, a predetermined pattern of data is placed on each of the output ports when the connected device is in a loopback mode. The pattern of data is detected at the input ports in response to the predetermined data placed on the output ports. The predetermined pattern on the output ports is compared with the detected pattern to determine the number of ports, P, of the connected one of the devices.

Buffer system

A method and apparatus for coupling a plurality of channels of a communications network to a node. The node includes a plurality of ports, each adapted for connection to a corresponding channel and a system interface adapted for connection to a plurality of node clients in the form of host computers, peripheral devices, network interfaces, etc. The node includes a receiver and transmitter dedicated to each port and common circuitry for controlling and processing frames received and/or transmitted by the plurality of ports. A frame prioritization circuit forwards frames received by a selected port to a frame handler for processing and a frame routing circuit routes frames processed by the frame handler to at least one of the ports associated with at least one destination node. The node further includes a frame header buffer associated with each port for temporarily storing the header of each frame received by the respective port prior to forwarding of the header to the frame handler.

Method and apparatus for reordering frames

A method and apparatus for reordering frames of a packet received at a node in an order other than the order in which the frames were transmitted. The node includes a port having a frame manager for providing an entry in memory for each frame received non-consecutively with respect to a previously received frame. A list of memory entries associated with a given packet provides a reassembly table. In one embodiment, each memory entry includes a sequence count identifying the previously received frame, a pointer to a memory location at which data associated with a set of one or more prior consecutively received frames are stored, and a data length value corresponding to a length of data associated with the set of prior consecutively received frames. The frames of the packet are reordered by processing entries in the reassembly table in ascending sequence count order.

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Foxboro, MA, United States of America

Miklos A Sandorfi