Telefonaktiebolaget Lm Ericsson (publ)

Nordic Semiconductor Asa

Mikko Lintonen

Marko Pessa

Jukka Kohola

Olli Varkki

Jarmo Väänänen

Janne Juusola

A voltage monitoring circuit portion is arranged to monitor a negative supply voltage (V) and comprises a negative voltage generator arranged to generate the negative supply voltage (V) and to output the negative supply voltage (V) at an output terminal. A capacitor is arranged so that a first capacitor plate is connected to the output terminal of the generator and to a reference node via a potential divider. The potential divider is arranged to produce a monitor voltage (V) between the resistors, where the reference node is supplied with a positive predetermined reference voltage (V). A comparator compares the monitor voltage (V) to a threshold voltage (V) and to produce an output signal having a first value when the monitor voltage (V) is below the threshold voltage (V) and having a second value otherwise. The negative voltage generator is enabled only when the output signal has its second value.

Voltage monitoring system for a negative supply voltage

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration. After the initial duration, the current mirror is disabled and the first transistor is rendered fully conductive.

Method and apparatus to minimize switching noise disturbance

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration. After the initial duration, the current mirror is disabled and the first transistor is rendered fully conductive.

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration.

A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.

Growing community of inventors

Oulu, Finland

Mikko Lintonen