Wisconsin Alumni Research Foundation

National Science Foundation

Global Supercomputing Corporation

Thalchemy Corporation

Mikko Herman Lipasti

Andrew Nere

Nam Sung Kim

Giulio Tononi

David John Palframan

Atif G Hashmi

Kemal Ebcioglu

Atakan Dogan

Reha Oguz Altug

Dibakar Gope

John F Wakerly

Gokul Subramanian Ravi

Eray Özkural

Atif Hashmi

A computer architecture suitable for out-of-order processors manages the problem of timing slack, in which an instruction completes before its clock cycle, by recycling that slack to allow the next succeeding instruction allowing that instruction to begin execution earlier. This recycling mechanism is enabled through the use of a transparent gating between execution units which allows data transfer before clock cycle boundaries and, in some cases, by aggressively issuing children instructions contemporaneously with their parent instruction after a grandparent instruction is issued.

Computer architecture allowing recycling of instruction slack time

Systems and methods achieving scalable and efficient connectivity in neural algorithms by re-calculating network connectivity in an event-driven way are disclosed. The disclosed solution eliminates the storing of a massive amount of data relating to connectivity used in traditional methods. In one embodiment, a deterministic LFSR is used to quickly, efficiently, and cheaply re-calculate these connections on the fly. An alternative embodiment caches some or all of the LFSR seed values in memory to avoid sequencing the LFSR through all states needed to compute targets for a particular active neuron. Additionally, connections may be calculated in a way that generates neural networks with connections that are uniformly or normally (Gaussian) distributed.

Efficient and scalable systems for calculating neural network connectivity in an event-driven way

The present inventors have recognized that proper utilization of reconfigurable event driven hardware may achieve optimum power conservation in energy constrained environments including a low power general purpose primary processor and one or more electronic sensors. Aspects of neurobiology and neuroscience, for example, may be utilized to provide such reconfigurable event driven hardware, thereby achieving energy-efficient continuous sensing and signature reporting in conjunction with the one or more electronic sensors while the primary processor enters a low power consumption mode. Such hardware is event driven and operates with extremely low energy requirements.

Reconfigurable event driven hardware using reservoir computing for monitoring an electronic sensor and waking a processor

An apparatus and method for filtering biased conditional branches in a branch predictor in favor of non-biased conditional branches are disclosed. Biased conditional branches, which are consistently skewed toward one direction or outcome, are filtered such that an increased number of non-biased conditional branches which resolve in both directions may be considered. As a result, more useful branches may be captured over larger distances, thereby providing correlations deeper in a global history. In addition, by tracking only the latest occurrences of non-biased conditional branches using a recency stack structure, even more distant branch correlations may be made.

Apparatus and method for bias-free branch prediction

A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.

Memory fault patching using pre-existing memory structures

A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.

Parallel hardware hypervisor for virtualizing application-specific supercomputers

Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable.

Growing community of inventors

Lake Mills, WI, United States of America

Mikko Herman Lipasti