Mitutoyo Corporation

Mikiya Teraguchi

Tetsuro Kiriyama

Kiyokazu Okamoto

Seiji Sakagami

Takanori Otsuka

Masayoshi Okamoto

Michio Nakamura

An linear encoder includes: a scale; a light-emitting element that emits light onto the scale; a detecting head that has a light-receiving element that receives the light emitted by the light-emitting element to be reflected or transmitted by the scale; and a connector connected to the detecting head via a cable. The connector comprises a display that displays a status of the light received by the light-receiving element and a connector controller that controls the display. The connector controller includes a display controller that controls the display in accordance with the intensity of the light received by the light-receiving element.

Optical encoder

An absolute type linear encoder includes: a scale including a plurality of tracks including a high-order and low-order tracks; and a detection head configured to detect a relative position to the scale; and a processing circuit configured to obtain the number of cycles of the low-order track by using a correction value obtained per correction pitch, the width of which is wider than the detection pitch, based on an error between tracks produced by a difference between the position of the high-order track to the detection head and the position of the low-order track thereto, output values of the high-order track and the low-order track, and a cyclic ratio of the low-order track to the high-order track, and obtain the position of the detection head to the scale based on the number of the cycles and the output value of the low-order track.

Absolute type linear encoder and method for adjusting position thereof

An absolute linear encoder includes a plurality of absolute scales aligned in the detection direction with absolute calibrations, a plurality of detectors for detecting the calibrations on the absolute scales, absolute position data generating portions of each scale for generating absolute position data of each detector, and a calculator for outputting an absolute position over the whole length of connected whole absolute scales adding the absolute position data of each detector and the distance between the detectors. The detectors are fixed at such intervals as to simultaneously detect the calibrations of the two absolute scales adjoining in a scale connecting section. Thus, the long absolute linear encoder which is easy to use is realized at low costs.

Absolute linear encoder

An encoder includes: a detector; an A/D converter for performing A/D conversion for a two-phase analog signal output from the detector; an error correction circuit for correcting an error of the two-phase analog signal; an interpolation circuit for performing interpolation from the corrected result of A/D conversion; a memory for storing correction data; and a central processing unit (CPU) having communication means. The result of A/D conversion of the two-phase analog signal is sent by the communication means to an external personal computer. The error of sine and cosine signals from a predetermined value is detected by the personal computer and is sent by the communication means. The encoder performs interpolation in which the error is corrected by using the received correction data. Thus, it is possible to perform signal adjustment without observing a display screen of an oscilloscope, while confirming a status of signal adjustment in a non-stepped manner. This enables optimum adjustment and confirmation to be performed, and reduces an interpolation error caused by adjustment of the encoder signal.

Encoder and signal adjustment method for the same

When data detected by an encoder is transmitted/received in predetermined cycles in a measuring device using a sampling control system for controlling a position or a speed at predetermined time intervals, positional data is divided so as to be output with deviation data output each time. The divided positional is reconstituted so as to transmit the positional data within a control cycle.

Data transmitting/receiving method and device for encoder

Output of an encoder are sampled by A/D converters 11a and 11b to be converted to N bits A-phase and B-phase digital data DA and DB. In a look-up table memory 12, reference phase angle data of phase divisions and average gradient vectors of changes in phase angle data within the phase divisions are stored, the phase divisions being addressed by the high order NU bits of data DA and DB. An arithmetic circuit 13 determines a vector inner product of an average gradient vector and phase-interpolating data represented by the low order NL bits of the data DA and DB to add the resultant to a phase angle data, thereby outputting an interpolated phase angle data.

Interpolation circuit for encoder having a look-up table memory with

An interpolation circuit of an encoder of which dynamic accuracy is improved is disclosed. The phase angle data detecting circuit 1 detects to store the phase angle data PH for each of the first clock CK1. The phase angle data PH is input to the updating circuit 2 in which the current data CNT is subtracted from the subsequent phase angle data PH so as to be updated. The differential data DX is limited within an upper limit to be added to the current data CNT. The integrating circuit 3 integrates the differential data DELTA1, whose upper limit is predetermined, by the second clock CK2 to generate the carry signal QUADEN at each timing when the integrated value leads to the period ratio of CK1 to CK2. The two-phase square wave generating circuit 5 generates two-phase square wave signals at each timing of the carry signal QUADEN. The over-speed detecting circuit 6 monitors the differential data DX to generate the over-speed alarm signal OSALM under a predetermined condition.

Interpolation circuit for encoder

Signals S.sub.j and S.sub.j-1 that are deviate from each other by a phase value of 2 .pi./M are generated by combining two sinusoidal detection signals. A reference signal .DELTA.S is generated which represents a difference between the signals S.sub.j and S.sub.j-1. An up-pulse or a down-pulse is generated every time the signal S.sub.j or S.sub.j-1 varies by .DELTA.S/n. An n-ary reversible ring counter outputs a first count value and a carry or borrow pulse by counting the up-pulse and the down-pulse, and the first count value is used to control the operation of generating the up-pulse or down-pulse. An M-ary reversible ring counter outputs a second count value by counting the carry pulse or the borrow pulse, and the second count value is used to control the operation of generating the signals S.sub.j and S.sub.j-1.

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Kawasaki, Japan

Mikiya Teraguchi