Sharp Kabushiki Kaisha Corporation

Mikiro Okada

Setsufumi Kamuro

Takaaki Hirano

Yasuhiro Hotta

Koji Komatsu

Akira Yamaguchi

Tsutomu Ashida

Junichi Tanimoto

Yukimine Shimada

Koji Imura

A semiconductor memory is arranged so that a first memory cell array is provided on one side of a set of a row decoder and word line driving circuits, while a second memory cell array is provided on an opposite side thereof. In the semiconductor memory thus arranged, the first memory cell array has less memory cells so that the first memory cell array has shorter word lines, so that more speedy access to a top data is achieved. By doing so, the access to the top address is made speedy in the high access mode such as the page mode or the serial access mode, with no increase in chip areas in the semiconductor memory and no increase in power consumption. Furthermore, in a semiconductor memory which stores first data requiring a comparatively higher read-out speed (for example, program data) and second data requiring a read-out speed lower than that of the first data, the first data is stored in the memory cell array having the shorter word lines, while the second data is stored in the memory cell array having the longer word lines. By doing so, read-out speeds in accordance with the types of stored data can be obtained, without wasteful power consumption in the word line driving circuits.

Semiconductor memory device capable of page mode or serial access mode

A semiconductor memory device according to the present invention includes: a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n &lt;2.sup.n +m&lt;2.sup.n+1 ; an address decoder for receiving an address signal of (n+l) bits and for specifying one of the (2.sup.n +m) memory cells in accordance with the address signal; an output circuit for outputting data stored in the memory cell specified by the decoding means; an empty address detecting circuit for receiving at least two bits of the address signal of (n+1) bits and for generating a detection signal which indicates whether the address signal represents an empty address or not; and a control circuit for receiving an enable signal and for generating a control signal for outputting the data stored in the specified memory cell in accordance with the enable signal, wherein the control circuit further receives the detection signal and generates a control signal for inhibiting the data from being output when the address signal specifies an empty address, regardless of the state of the enable signal.

Semiconductor memory device

A read-only memory includes columns of memory cell arrays, a plurality of banks formed by dividing each column of the memory cell arrays along the columns, sub-bit lines disposed between adjacent banks situated along the rows and connected to a transistor of each memory cell, and main-bit lines disposed between every two other columns of the memory cell arrays and extending along the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks situated along the rows, and one end of each center sub-bit line being connected to a first main-bit line through a first selector transistor, the first main-bit line passing through one side of the set to which the center bit-line belongs, and the other end of the sub-bit line being connected to a second main-bit line through a second selector transistor, the second main-bit line passing through the other side of the set to which the center sub-bit line belongs, the two outer sub-bit lines being directly connected to the main-bit lines adjacent to the set of banks, respectively.

Read-only memory

A matrix type semiconductor memory device with a higher complexity is provided which includes a p-type (or an n-type) semiconductor substrate, a plurality of n-type (or p-type) semiconductor regions formed as strips that are arranged in parallel at predetermined spacings in the surface of the substrate, the semiconductor regions provide alternating source regions and drain regions which define gate regions between the alternating regions, a first gate insulating film formed in a plurality of strips on the surface of the substrate at predetermined spacings which intersect the plurality of semiconductor regions, a plurality of first gate electrodes formed on each of the strips of the first gate insulating film, a second gate insulating film formed in a plurality of portions on the exposed surfaces of the substrate between the strips of first gate insulating film, and a plurality of second gate electrodes formed on each of the portions of the second gate insulating film without contacting the first gate electrodes. Thereby, a matrix of MIS semiconductor cells is formed, with each of the cells being provided at the intersection of each of the gate regions with one of the first and second electrodes, and the gate regions of some of the cells are selectively doped with a p-type (or an n-type) impurity substance at a higher concentration than the substrate.

Semiconductor memory device with compact ROM memory cells

A reference voltage generating circuit comprises a depletion type MOS transistor of which the gate and the drain are connected to a power source and an enhancement type MOS transistor of which the gate and the drain are connected to the source of the depletion type MOS transistor through a junction from which a reference voltage is outputted. This reference voltage is adapted to be applied to the gate of an enhancement type MOS transistor in a load circuit composed of enhancement/depletion MOS transistors and serving to drive a logical circuit.

Reference voltage generating circuit for enhancement/depletion MOSFET

A peripheral unit for a microprocessor system connected to a microprocessor comprises means for selecting whether an operation of the peripheral unit is to be halted in response to an inputted signal, and means for prohibiting the supply of a signal for activating the peripheral unit in response to the output of the selecting means. The peripheral unit, further, comprises means for canceling the operation of the prohibiting means to supply the signal for activating the peripheral unit in response to a second inputted signal. The peripheral unit and the microprocessor are constructed of CMOS transistors.

Peripheral unit for a microprocessor system

A serial input/output device includes a CMOS shift register having a plurality of D-type flip-flops. A detection circuit is associated with the CMOS shift register in order to detect whether the transfer data exists in the CMOS shift register. A gate circuit is provided for applying a transfer clock signal to the CMOS shift register only when the transfer data exists in the CMOS shift register, thereby minimizing the power consumption.

Growing community of inventors

Nara, Japan

Mikiro Okada