Hitachi, Ltd.

Mikio Yamagishi

Kazuo Koide

Akira Yamagiwa

Noboru Masuda

Tetsuo Nakano

Kazunori Nakajima

Bunichi Fujita

Seiichi Kawashima

Toshihiro Okabe

Kazumichi Yamamoto

Tetsuya Fukuoka

Kazutaka Mori

A semiconductor integrated circuit device is provided with a diagnosis circuit, which does not increase the delay of a logic element in normal operation. In a latch provided at the output of a memory or at the input of a logic stage, a signal selector is provided in the feedback loop of the latch. The selector is switched in correspondence with the operation mode, such that it transfers the feedback signal in normal operation, while it transfers the test signal in a test mode, in order to prevent the delay from increasing in the signal selector on the main path in normal operation.

Semiconductor integrated circuit device having test circuit

A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

Variable delay circuit and clock signal supply unit using the same

A semiconductor integrated circuit device includes an interface corresponding to a relatively high signal level; an interface corresponding to a relatively low signal level; and an internal circuit made responsive to a signal through either interface for generating a signal to be transmitted to the other interface. The interface corresponding to a relatively high level, the internal circuit, and a drive control circuit constituting the input circuit and output circuit of the interface corresponding to a relatively low level are operated by an operating voltage corresponding to the relatively high level. An output element of the output circuit in the interface corresponding to a relatively low level, which is to be driven by the drive control circuit, is operated by an operating voltage corresponding to the relatively low level.

Semiconductor integrated circuit device capable of outputting a

A semiconductor integrated circuit device comprises a plurality of peripheral power supply lines extending along the periphery of an internal circuit region formed in a semiconductor chip. Bonding pads are arranged outside of the peripheral power supply lines, wherein the wiring layers used in the peripheral power supply line arranged at the outermost periphery are made less by one than those used in the inner peripheral power supply line adjacent to the outermost peripheral power supply line. Reduced wiring layers are formed with power leading lines for connecting the inner peripheral power supply line and the bonding pads. Moreover, the power leading lines for connecting the outermost peripheral power supply lines and the bonding pads are formed of the same wiring layer as that of the outermost peripheral power supply line. The semiconductor integrated circuit device is further constructed such that there are arranged along the peripheral of the internal circuit region a plurality of I/O cells and high drive power output buffer circuits which include two or more adjacent ones of the plurality of I/O cells and which are adapted to be fed with the supply voltages from the peripheral power supply lines. Moreover, predetermined ones of external terminals assigned to the plurality of I/O cells constituting the high drive power output buffer circuits are used as terminals for feeding the supply voltages to the plurality of peripheral power supply lines.

Semiconductor integrated circuit device

In order to reduce undesirable output noise, an output circuit is provided which includes a first output MOSFET which is interposed between an output terminal and a first power source voltage, and a second output MOSFET which is interposed between the output terminal and a second power source voltage. In particular, in accordance with one aspect of the invention, a feedback circuit is interposed between the output terminal and the gate of the first output MOSFET or/and between the output terminal and the gate of the second output MOSFET to negatively feedback voltage to provide a gentle level change for the output voltage. In other embodiments, a short-circuit arrangement is provided which is interposed between the gate and source of the first output MOSFET or/and between the gate and source of the second output MOSFET. The short-circuit arrangement is temporarily held in a transferring state at the initial stage of a process in which the corresponding first or second output MOSFET is turned on to provide the desired gentle level change.

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Ohme, Japan

Mikio Yamagishi