Renesas Electronics Corporation

Renesas Technology Corp.

Mikio Tsujiuchi

Tatsunori Murata

Toshiaki Iwamatsu

Shigeto Maegawa

Tetsuya Nitta

Shigenobu Maeda

Takuji Matsumoto

Yuuichi Hirano

Yosuke Takeuchi

Ryoji Matsuda

Keisuke Tsukamoto

Kenichi Mori

Masayoshi Tarutani

Kouji Tanaka

Shunji Kubo

Kazuyuki Omori

Yasuki Yoshihisa

A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Semiconductor device with improved short circuit capability

A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an ndrain region toward an nsource region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the ndrain region toward the nsource region.

Semiconductor device and method for manufacturing the same

In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.

Semiconductor device

In a semiconductor device, at least one of the ratio (collector contact area/collector active area) in the High Side IGBT and the ratio (contact area on pregion/pregion area) is higher than the ratio in the Low Side IGBT. Thus, it is possible to develop without substantial changes and reduce the development burden.

To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed over the bottom electrode so as to cover the MTJ element part, wherein the bottom electrode is formed by amorphized metal nitride and the protection film is formed by an insulating film containing nitrogen.

Semiconductor device including a magnetic tunnel junction and method of manufacturing the same

A semiconductor device excellent in the magnetic shielding effect of blocking off external magnetic fields is provided. The semiconductor device includes: an interlayer insulating film so formed as to cover a switching element formed over a main surface of a semiconductor substrate; a flat plate-like lead wiring; a coupling wiring coupling the lead wiring and the switching element with each other; and a magnetoresistive element including a magnetization free layer the orientation of magnetization of which is variable and formed over the lead wiring. The semiconductor device has a wiring and another wiring through which the magnetization state of the magnetization free layer can be varied. In a memory cell area where multiple magnetoresistive elements are arranged, a first high permeability film arranged above the magnetoresistive elements is extended from the memory cell area up to a peripheral area that is an area other than the memory cell area.

Semiconductor device and semiconductor device assembly

In a semiconductor device, a body thick film transistor and a body thin film transistor having a different body film thickness are formed on the same SOI substrate (silicon support substrate, buried oxide film and silicon layer). The body film is formed to be relatively thick in the body thick film transistor, which has a recess structure where the level of the surface of the source/drain regions is lower than the level of the surface of the body region, and thus, the SOI film in the source/drain regions is formed to be as thin as the SOI film in the body thin film transistor. On the other hand, the entirety of the SOI film is formed to have a relatively thin film thickness in the body thin film transistor. In addition, the source/drain regions are formed to penetrate through the silicon layer.

Semiconductor device and manufacturing method for the same

To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element.

To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion. The thickness of the sidewall portion is made greater than that of the bottom wall portion.

Semiconductor device and manufacturing method thereof

To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NHbut composed of SiH/N/helium (He). The film forming temperature is set at from 200 to 350&#xb0; C. More ideally, a flow rate ratio of He to SiHis set at from 100 to 125.

Manufacturing method of semiconductor device having memory element with protective film

Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed.

Semiconductor device having memory element with stress insulating film

The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NHor Has pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm; and the film forming temperature is set in the range of 200&#xb0; C. to 350&#xb0; C.

Growing community of inventors

Tokyo, Japan

Mikio Tsujiuchi