Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Mikio Sakurai

Susumu Tanida

Takahiko Fukiage

Kazuhiro Sakemi

Yasuhiro Konishi

Yasuhiko Tsukikawa

Yutaka Ikeda

Shigeru Mori

Takeshi Kajimoto

Yoshinori Inoue

Yasuhiro Matsumoto

Kenji Tokami

Masaya Nakano

Hisao Kobashi

Tooru Ichimura

Miki Nakahira

The power supply tuning circuit in accordance with the present invention is provided with a plurality of power supply circuits. Each power supply circuit includes a latch circuit. The latch circuit records a tuning signal. The recorded tuning signal causes the corresponding transistor to switch on/off. In this manner, pseudo-tuning is performed. After a tuning signal is supplied to the latch circuit, the tuning signal is supplied to another power-supply circuit. Thus, pseudo-tuning can be preformed simultaneously for a plurality of power supply circuits.

Semiconductor integrated circuit device having pseudo-tuning function

The present invention relates to a synchronous semiconductor memory device and an object of the present invention is to provide a synchronous semiconductor memory device in which an operation mode such as a set burst length would not be lost even at the power off. Here, the synchronous semiconductor memory device according to the present invention includes non-volatile memory for storing operation mode and controlling data reading operation and data writing operation in accordance therewith.

Synchronous semiconductor memory device

A clock buffer in a semiconductor memory device includes two kinds of interface circuits, i.e., an LVTTL interface and an SSTL interface. When the semiconductor memory device is set to a specific mode (self-refresh mode) for suppressing a power consumption, the LVTTL is used for taking in an external signal. In a mode other than the self-refresh mode, the SSTL interface is used to take in an externally supplied signal. Thereby, a current can be suppressed in the specific mode.

Semiconductor memory device provided with an interface circuit consuming

When refresh of a memory bank having a plurality of array banks is instructed, a refresh control circuit carries out the refresh by saving a row address latched in a row address latch circuit and a bank activation signal supplied to a bank drive unit respectively in a row address saving circuit and a bank activating information saving circuit. After the refresh completes, each array bank is returned to its original state before the refresh instruction is supplied, according to the saved row address and bank activate information. Accordingly, a synchronous semiconductor memory device in which the penalty at the time of the refresh is reduced is provided.

Multi-bank synchronous semiconductor memory device with easy control

An act signal generation circuit in a synchronous semiconductor memory device includes an act command latch circuit, an act command output circuit, and an act command control circuit. The act command latch circuit latches externally applied active command information. The act command output circuit responds to an enable signal to output an act initiation signal that renders a bank active. The act command control circuit responds to level transition of an external control signal in a test mode to alter the level of the enable signal. As a result, the active command information can be delayed and then transmitted to a bank.

Synchronous semiconductor memory device including a circuit for

A reset signal generation circuit included in an output control circuit ANDs a reset signal for resetting complementary data buses for transferring data to a second output stage at prescribed timing and an internal control signal corresponding to a read mask signal and outputs a reset signal for resetting other complementary data buses for transferring the data to a final output stage. Thus, invalid data is reset on the complementary data buses.

Synchronous semiconductor memory device having function of inhibiting

A plurality of memory banks are activated to select a memory cell in response to a bank select signal from a bank select signal generating circuit. When a special mode of operation is designated, a mode setting circuit activates all of bank select signals from the bank select signal generating circuit to simultaneously drive all memory banks to active/inactive state. Thus, a multi-bank, a synchronous semiconductor memory device capable of accessing memory cells at high speed and efficiently selecting memory cells is obtained.

Multi-bank synchronous semiconductor memory device

A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped.

Synchronous semiconductor device having circuitry capable of surely

A read register and a data transfer circuit are provided to implement two separate data transfer paths with respect to a preamplifier, for alternately transferring data through these two paths. Thus, the data can be transferred with no data collision in each clock cycle. The data are transferred at a high speed every clock cycle regardless of the bank number and the CAS latency in a multi-bank synchronous memory device.

One of the two data input/output line pairs and the selected bit line pair included in a memory cell array are connected by a column switch, and the read out data is output to a preamplifier through a switching circuit. A data input/output line pair of the data input/output line pairs which is not used for data transmission is equalized by an equalizing circuit. Therefore, data readout and equalizing operation are carried out in parallel, thereby achieving high-speed data readout.

Semiconductor memory device utilizing two data line pairs and realizing

A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.

Semiconductor device having an improved immunity to a short-circuit at a

A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Semiconductor device including signal generating circuit with level

A MOS-type semiconductor clamping circuit includes a semiconductor substrate receiving a substrate potential, a well isolated electrically from the substrate potential, and MOS-type transistors formed in the well. Those transistors are connected with each other in series, each transistor has its gate connected to its drain, and a stable potential different from the substrate potential is applied to the well.

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Hyogo, Japan

Mikio Sakurai