Sony Corporation

Sony Semiconductor Solutions Corporation

Mikio Oka

Yasuo Kanda

Takashi Yokoyama

Yutaka Higo

Kaoru Koike

Kenji Noguchi

Hidetoshi Ohnuma

Hidetoshi Oishi

Kensuke Tsuchiya

A nonvolatile memory cell includes a resistance-change nonvolatile memory elementand a selection transistor TR. One end of the nonvolatile memory elementis connected to one source/drain regionA of the selection transistor TR and is connected to a write line WR. The other source/drain regionB of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory elementis connected to a bit line BL.

Nonvolatile memory cell, nonvolatile memory cell array, and information writing method of nonvolatile memory cell array

A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Semiconductor device and electronic apparatus including the same

Provided is a semiconductor device having a structure suitable for higher integration. The semiconductor device includes a transistor that includes a gate section, a first diffusion layer, and a second diffusion layer. The semiconductor device further includes a first electrically-conductive section a second electrically-conductive section that is electrically insulated from the first electrically-conductive section, a first storage element that is located between the first diffusion layer and the first electrically-conductive section and is electrically coupled to each of the first diffusion layer and the first electrically-conductive section, and a second storage element that is located between the second diffusion layer and the second electrically-conductive section and is electrically coupled to each of the second diffusion layer and the second electrically-conductive section.

Semiconductor device and imaging unit

A semiconductor device of the present disclosure includes: a first gate electrode that includes a first main line section and one or a plurality of first sub line sections, in which the first main line section extends in a first direction in a first active region of a semiconductor substrate, and segments the first active region into a first region and a second region, and the one or the plurality of first sub line sections extends from the first main line section in a second direction intersecting the first direction in the first region, and segments the first region into a plurality of sub regions including a first sub region and a second sub region; a first memory element that includes a first terminal, and a second terminal coupled to the first sub region of the semiconductor substrate, and is configured to be set in a first resistive state or a second resistive state; and a second memory element that includes a first terminal, and a second terminal coupled to the second sub region of the semiconductor substrate, and is configured to be set in the first resistive state or the second resistive state.

Semiconductor device

The present disclosure relates to a semiconductor storage device, a driving method, and an electronic device capable of suppressing a layout area and improving reliability. A semiconductor storage device is provided with one or more selection transistors, a resistance change element one end of which is connected to a bit line and the other end of which is connected to a drain terminal of a selection transistor, the resistance change element a resistance value of which changes by a current of a predetermined value or larger allowed to flow, and a write control unit connected to a connection point between the selection transistor and the resistance change element and controls the current flowing through the resistance change element when data is written in the resistance change element. The present technology is applicable to, for example, a non-volatile memory provided with a storage element configured by a magnetic tunnel junction.

Semiconductor storage device, driving method, and electronic device

An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

Memory cell and array having device, P-type transistor and N-type transistor

A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.

Mask pattern design method and semiconductor manufacturing method and semiconductor design program

A pattern correction method includes: a correction step of performing pattern correction on a semiconductor circuit pattern having plural transistors as component elements; an order of priority recognition step of recognizing an order of priority set with respect to the plural transistors prior to the pattern correction at the correction step; and a condition adjustment step of adjusting correction conditions for the pattern correction with reference to the transistor having a high priority recognized at the order of priority recognition step in the pattern correction at the correction step.

Growing community of inventors

Kanagawa, Japan

Mikio Oka