Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Mikio Nishio

Tomoyasu Murakami

Masayuki Endo

Kazuhiko Hashimoto

Shin Hashimoto

Toyokazu Fujii

Mitsuru Sekiguchi

Akemi Kawaguchi

Mitsunari Satake

Susumu Akamatsu

Akito Uno

Chiaki Kudoh

Yasusi Okuda

The present invention provides a thin film semiconductor element which is small in area with high on-current enough to be suitable for the power saving, miniaturization, and high definition display of a device. According to the present invention, an outer shape of a semiconductor thin film is processed and regions (a channel region, a source region, and a drain region) in the semiconductor thin film are formed by using, as masks, other element components such as a gate electrode. Specifically, ion-implanted regions are formed by implanting impurity ions into predetermined regions of the semiconductor thin film using, as a mask, the gate electrode overlapped on the thin film via an insulation film. Thereafter, the semiconductor is processed into a predetermined shape by etching using, as masks, previously formed element components such as the gate electrode.

Thin-film semiconductor element and method of producing same

A polishing pad used for polishing a film on a semiconductor wafer and made of a plastic includes a polishing pad body, and a large number of convex portions, which are provided on the surface of the polishing pad body just like so many islands and each have a flat top surface. An average length L of respective sides or diameters of the convex portions on the top surface thereof is in the range from 0.1 mm to 5.0 mm, both inclusive; an average height H of the convex portions is in the range from 0.1 mm to 0.5 mm, both inclusive; and H.ltoreq.L.ltoreq.2S is met, where S is an average space between the convex portions.

Polishing pad for semiconductor wafer and method for polishing

An apparatus for holding a substrate to be polished comprises: a rotating rotary shaft; a substrate holding head in the form of a disc; a sealing member provided to the back face of the substrate holding head; a guiding member which is provided to the back face of the substrate holding head to be located outside the sealing member; and a fluid flow path which vertically penetrates the inside of the substrate holding head. The fluid flow path allows an air under pressure introduced from the upper end side thereof to flow out through the opening at the lower end thereof to a space. The sealing member is formed with a ventilation body having a large number of successive vent openings in the inside such as nonwoven fabric.

Apparatus for holding substrate to be polished

A rotatable platen has a polishing pad adhered to the top surface thereof. A carrier for holding a substrate and a slurry supply pipe for supplying an abrasive slurry onto the near-center region of the polishing pad are provided above the polishing pad. Two lamps for partially irradiating the surface of the polishing pad with visible light or infrared light are provided at respective locations above the polishing pad and upstream of the carrier in the direction of rotation of the platen. Of the area of the polishing pad in contact with the substrate, a region closer to the center of rotation of the polishing pad and a region farther away therefrom are heated by the two lamps.

Polishing method and polishing apparatus

An elastic polishing pad is adhered to a surface of a flat substrate holder of a platen. A substrate holding head which holds and rotates a semiconductor substrate is provided above a first region extending from the central portion to peripheral portion of the polishing pad. The semiconductor substrate rotated by the substrate holding head is pressed against the first region of the polishing pad. A slurry is dropped in a prescribed amount from an abrasive supply pipe onto the polishing pad. Pad pressing means for pressing the polishing pad is provided above a second region extending from the central portion to peripheral portion of the platen. The pad pressing means has a disk-shaped pad pressing plate and a rotary shaft for holding the pad pressing plate.

Method and apparatus for polishing semiconductor substrate

On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.

Alignment chips positioned in the peripheral part of the semiconductor

An elastic polishing pad is adhered to the top face of a rotatable table. Above the table is provided a substrate holding apparatus for holding a substrate. The substrate holding apparatus comprises a rotary shaft, a substrate holding head in the form of a disc which is provided integrally with the lower edge of the rotary shaft, a sealing member in the form of a ring which is made of an elastic material and fastened to the peripheral portion of the lower face of the substrate holding head, and a guiding member in the form of a ring which is fastened to the back face of the substrate holding head to be located outside the sealing member. A fluid under pressure is introduced into a fluid flow path formed in the rotary shaft from one end thereof and supplied to a space from the other end of the fluid flow path so as to press the substrate against the polishing pad.

Apparatus for polishing substrate using resin film or multilayer

Mehtod and aparatus for polishing semiconductor substrate

A polishing pad is adhered to the top surface of a flat polishing pad holder of a platen. A substrate holding head for holding and rotating a semiconductor substrate is provided above the platen. The semiconductor substrate is rotated and pressed against the polishing pad on the platen. A slurry is supplied in a prescribed amount from a slurry supply pipe onto the polishing pad. A slat-like slurry pushing member for pushing the slurry to a central portion of the platen is provided slidably over the polishing pad. The slurry pushing member is fixed so that an inner portion thereof in a radial direction of the platen is downstream of an outer portion thereof in the radial direction of the platen in the direction of rotation of the platen during polishing.

A contact hole and a wiring groove are formed in an insulating layer formed on a semiconductor substrate. A silver layer is formed inside of the contact hole and the wiring groove and on the insulating layer with the use of an electroless plating bath comprising: silver nitrate containing silver ions; tartaric acid serving as a reducing agent of the silver ions; ethylenediamine serving as a complexing agent of the silver ions; and metallic ions of tetramethylammoniumhydroxide serving as a pH control agent. Then, the silver layer on the insulating layer is removed by a chemical and mechanical polishing method such that an embedded wiring is formed in each of the contact hole and the wiring groove.

Electroless plating bath used for forming a wiring of a semiconductor

Apparatus for holding substrate to be polished and apparatus and method

A MOS transistor consists of a gate insulating film, a gate electrode, a pair of sidewall spacers on the side faces of the gate electrode, lightly doped source/drain regions, and heavily doped source/drain regions, which are located below the sidewall spacers. Between the sidewall spacers and an isolation are formed concave portions. On a silicon substrate in the concave portions are formed insulating films for capacitance reduction. On the insulating films for capacitance reduction are formed withdrawn electrodes. The heavily doped source/drain regions are electrically connected to the withdrawn electrodes between the sidewall spacers and the insulating films for capacitance reduction. Consequently, a pn junction capacitance beneath the source/drain regions is reduced, while the contact area between the source/drain regions and wiring is surely obtained, thereby achieving higher integration of the MOS transistors.

Growing community of inventors

Osaka, Japan

Mikio Nishio