Sony Corporation

Mikio Mukai

Yutaka Hayashi

Yasutoshi Komatsu

Toshio Kobayashi

Takeshi Kobayashi

Shunkichi Shimizu

Masahiko Einaga

A memory cell with a stored charge on its gate comprising; (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, (E) a first non-linear resistance element having two ends, one end being connected to the first gate, and (F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.

Memory cell with stored charge on its gate and a resistance element having non-linear resistance elements

A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

Semiconductor memory cell

A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Semiconductor memory cell and method of manufacturing the same

Impurity profiles Pi,and Ps,are determined for the same conditions by a reference acquiring means and a simulation capable of producing a result faster than the reference acquiring means, respectively. Errors between the impurity profile Pi,determined by the reference acquiring means and the impurity profile Ps,determined by the simulation are determined. An impurity profile Psx is calculated for another kind of conditions by the simulation, and a new impurity profile Psx&prime; is calculated by correcting the impurity profile Psx so as to reflect the errors.

Semiconductor simulation method

A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control; the first transistor having source/drain regions constituted of a first region and a fourth region, and a channel forming region constituted of a surface region of a third region; the second transistor having source/drain regions constituted of a second region and the third region, and a channel forming region constituted of a surface region of the first region; the junction-field-effect transistor having gate regions constituted of the fifth region and a portion of the third region facing the fifth region, a channel region constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region, and source/drain regions constituted of the fourth region.

Provided is a semiconductor memory cell which requires no refreshing operation for retaining information. The semiconductor memory cell comprises a first transistor TR,having a first conductivity type, a second transistor TR,having a second conductivity type and a MIS type diode DT for retaining information, wherein one source/drain region of the first transistor TR,corresponds to the channel forming region CH,of the second transistor TR,, one source/drain region of the second transistor TR,corresponds to the channel forming region CH,of the first transistor TR,, one end of the MIS type diode DT is formed of an extending portion of the channel forming region CH,of the first transistor TR,, and the other end of the MIS type diode DT is constituted of an electrode which is formed of an electrically conductive material and connected to a third line having a predetermined potential.

A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, and (E) a non-linear resistance element having at least two ends with one end connected to the first gate.

Memory cell with stored charge on its gate and process for the

A semiconductor memory cell includes a read-out transistor of a first conductivity type which has source/drain regions constituted by a second conductive region and a third semiconducting region, a channel forming region constituted by a surface region of a second semiconducting region, and a conductive gate formed on a barrier layer; a switching transistor of a second conductivity type which has source/drain regions constituted by a first conductive region and the second semiconducting region, a channel forming region constituted by a surface region of a first semiconducting region, and a conductive gate formed on a barrier layer; and a current controlling junction-field-effect transistor of a first conductivity type which has gate regions constituted by a third conductive region and a portion of the second semiconducting region, a channel region constituted by a portion of the third semiconducting region, and one source/drain region extended from one end of the channel region, being constituted by a portion of the third semiconducting region, and another source/drain region extended from the other end of the channel region, being constituted by a portion of the third semiconducting region.

Semiconductor memory cell and its fabrication process

A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Method for forming field effect transistor having multiple gate

A base is etched using as mask a first masking layer which has been patterned, softened and deformed. Then, the first masking layer is eroded, a second masking layer is selfaligningly formed only on bare portions of the base, and the base is again etched using as mask the second masking layer. Within a pitch of the first masking layer, the base can thus be etched in two regions which are separated from each other. These treatments can also be conducted in two directions.

Method of forming pattern

A lower-layer interconnection and an upper-layer interconnection formed on the lower-layer interconnection through an interlayer insulating film interposed therebetween are connected to each other by a plurality of contact plugs the interconnections and the contact plugs providing a plurality of conductive paths. The lower-layer interconnection is made of a conductive material having a resistivity higher than the upper-layer interconnection. At least one of the conductive paths provided in the lower-layer interconnections is shorter than the other conductive paths, and the contact plug which provides the shorter conductive path has a lower resistance than the contact plugs which provide the other conductive paths. With this arrangement, the contact plug which provides the shorter conductive path is prevented from suffering an increased current density, and the current densities in the contact plugs are uniformized.

Joint structure for multilayer interconnections

Field effect transistor having multiple gate electrodes surrounding the

A method of manufacturing a lateral insulated gate field effect transistor comprises the steps of forming a projecting portion on a first major surface of a semiconductor substrate, forming a pair of gate portions each of which is formed in each side of the projecting portion, forming an insulating layer on the resulting surface of the semiconductor substrate by burying the projecting portion and the pair of gate portions, and removing the semiconductor substrate from a second major surface of the semiconductor substrate to a position of the insulating layer in which the projecting portion is buried to expose the bottom surface of the projecting portion.

Method of manufacturing a Xmos insulated transistor

A lateral insulating gate type field effect transistor can be manufactured with ease reliably by using a semiconductor substrate having excellent crystal property. A projected portion (2) is formed on a first major surface side of a semiconductor substrate (1). A first gate portion (3) having a width (length) smaller than that of the projected portion (2) is formed on the projected portion (2). An insulating layer (4) is formed on the whole surface of the semiconductor substrate (1) so as to bury the first gate portion (3). The semiconductor substrate (1) is removed horizontally from its second major surface side, i.e., from the opposite side of the side of the projected portion (2) to a position (a) at which the insulating layer (4) is formed so as to bury the projected portion (2) is exposed. A second gate portion (5) is formed on such exposed surface.

Growing community of inventors

Kanagawa, Japan

Mikio Mukai