Mitsubishi Denki Kabushiki Kaisha

Mikio Kyomasu

Yoshiharu Nakao

Mitsuo Nakayama

A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V.sub.G -V.sub.TH &gt;V.sub.D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.

Semiconductor memory device

In the disclosed FAMOS semiconductor non-volatile memory a source and a drain region of the p.sup.+ type are disposed in an n semiconductor layer to form a gate region between them. The main face of the semiconductor layer is coated with a silicon dioxide film in which a polycrystalline silicon gate is buried to bridge the source and drain regions. An n.sup.+ type high doped semiconductor region is disposed in the semiconductor layer only under the silicon gate to form a pn junction with the drain region. Thus the pn junction is normal to the main face of the semiconductor layer.

Growing community of inventors

Itami, Japan

Mikio Kyomasu