Fujitsu Corporation

Mikio Itoh

Akihiko Hoshino

Nobuhiko Kuribayashi

Akira Yoshida

Hidekiyo Ozawa

Yuji Oinaga

Hirofumi Morita

Suijin Takeda

Nobuo Uchida

Tomoyuki Suganuma

When an amount of write data instructed by an upper-level system is small, a plurality of disk units are accessed individually and data split in sectors is written therein (Level 5 RAID). When an amount of write data instructed by the upper-level system is large, the plurality of disk units are accessed in parallel and data split in sectors is written therein (Level 3 RAID). When a disk unit in an array, to which a setup instruction is issued according to a processing request sent from the upper-level system, returns a fault reply, an ID management table is used to allocate an auxiliary disk instead of the failing disk unit. After the allocation, data is restored to the replacement disk using the data in normal disk units in the same rank. In a dual-port access configuration, when two transactions access disk units connected to the same port, a deadlock may occur depending on the access procedure. It is checked if the conditions for a deadlock are established, so that access will be obtained according to a procedure for preventing or avoiding a deadlock.

Apparatus for controlling data writing into a disk array system

In a data processing system including at least two processing units having different throughputs for performing sequential access upon a main storage unit, the number of elements of the main storage unit simultaneously accessed by the processing units is different, or the sequence of elements accessed by one of the processing units is reversed, thereby substantially improving the input/output throughput for the main storage unit.

Data processing system for processing units having different throughputs

An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.

Main storage access priority control system that checks bus conflict

A shift register which is formed by a memory, the number of shift stages of the shift register is determined by the count value of a counter and designating a read address of the memory by a value obtained by subtracting an arbitrary constant from the count value of the counter through an operator. A multiplexer is provided at the input side of the operator. Output data, obtained by selecting a constant for determining the number of shift stages of the counter and a scan address in accordance with a scan enable signal, are provided to the operator. When the constant for determining the number of shift stages of the counter is input, the operation of the shift register is carried out and when the scan address is input, the content of each stage of the shift register is scanned out.

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Yokohama, Japan

Mikio Itoh