Fujitsu Corporation

Mikio Hondou

Toshio Yoshida

Iwao Yamazaki

Shuji Yamamura

Ryuji Kan

Noriyuki Takahashi

A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Processing apparatus and control method performing taylor series operation associated with executing floating point instruction

A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Cache memory having sector function

A priority control registerdynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unitand retaining state of the memory request in the REQ_BUFobtained by each of determination circuitsthrough #. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM modulecan be realized.

Memory control device and method

A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs*rs)|(rs[0]&#x3c;&#x3c;63) and a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs[0])? 1.0: rs)^(rs[1]&#x3c;&#x3c;63), or a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs*rs)|((&#x2dc;rs[0]&#x3c;&#x3c;63) and a fourth trigonometric function operation auxiliary instruction for defining the operation of rd=((rs[0])? rs: 1.0)^((rs[1]^rs[0])&#x3c;&#x3c;63)).

Processing unit

A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions

A processor equipped with a pre-fetch function comprises: first layer cache memory having a first line size; second layer cache memory that is on the under layer of the first layer cache memory and that has a second line size different from the first line size; and a pre-fetch control unit for issuing a pre-fetch request from the first layer cache memory to the second layer cache memory so as to pre-fetch a block equivalent to the first line size for each second line size.

Processor equipped with a pre-fetch function and pre-fetch control method

A branch prediction apparatus reads out a branch history tableby an index calculated by the output of a branch history registercontaining a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units-for detecting the appearance frequency of a branch instruction with a different address and data width modification unitsandfor modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.

Branch prediction apparatus, its method and processor

An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.

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Kawasaki, Japan

Mikio Hondou