Nec Corporation

Mikio Fukushi

Hideho Tomita

In a DPLL circuit used in a receiver for radio data communication employing the GMSK modulation system, a data latch circuit 23 and subtractor 24 find the phase information difference for each symbol from the incoming phase data. A modulation component removal circuit 25 removes the modulation component from the phase information difference. A frequency error calculating circuit 26 integrates the phase information difference over an interval of n symbols, multiplies this integrated value by 1/n, and takes the result as the mean frequency error value for the interval of n symbols, and then outputs this to loop filter 32. A phase error calculating circuit 27 further integrates over an interval of n symbols the integrated value from the frequency error calculating circuit, and multiplies the result by 2/n. Adder 28 adds an initial phase latched by a data latch circuit 22 to the output of the phase error calculating circuit, and outputs the result to NCO 33 as the phase error value. Operation of loop unit 36 is commenced with a timing that is preset by the mean frequency error value and phase error value.

Digital PLL circuit and actuating method

In a modulating system, a converting unit generates first and second quadrature signals based on a transmission data signal in synchronous with a transmission clock signal. First and second filters perform band limitation to the first and second quadrature signals to generate first and second band-limited quadrature signals. An oscillator generates a sine wave signal and a phase shifter phase-shifts the sine wave signal from the oscillator to generate first and second phase-shifted sine wave signals. A phase difference between them is .pi./2, and the first phased-shifted sine wave signal precedes the second phased-shifted sine wave signal in the phase. First and second multipliers multiply the first and second phase-shifted sine wave signals by the first and second band-limited quadrature signals to generate first and second multiplied signals, respectively. An adder synthesizes the first and second multiplied signals to generate an synthesis signal. Then, a limiter for limiting an amplitude of the synthesis signal to a predetermined level.

Modulation of transmission data signal in sychronous with transmission

A digital PLL apparatus includes a synchronization integrating circuit, an angle calculating circuit, and a digital PLL circuit. The synchronization integrating circuit determines a symbol timing by obtaining the maximum amplitude point of a correlation level during reception of a preamble. The angle calculating circuit outputs a phase .theta.c by performing an angle calculation every symbol timing determined by the synchronization integrating circuit. The digital PLL circuit receives the phase .theta.c from the angle calculating circuit and operates a phase locked loop, thereby obtaining an output phase.

Digital phase locked loop assembly

A demodulator for radio data communications is provided, which is capable of an optimum demodulation operation in response to the environmental condition under which communications are made independent of the preamble length. A phase angle calculator calculates a phase angle of the input signal. A frequency offset calculator calculates an offset of a carrier frequency of the input signal. A PLL generates a compensated phase angle of the input signal to compensate the frequency offset. A first detector detects the input signal using the uncompensated phase angle to generate a first detected signal. A second detector detects the input signal using the compensated phase angle to generate a second detected signal. A first phase distortion calculator calculates a phase distortion of the first detected signal. A second phase distortion calculator calculates a phase distortion of the second detected signal. A phase distortion comparator compares the phase distortions of the first and second detected signals to generate a result signal. A selector selects an output from one of the first and second detectors according to the result signal.

Phase demodulator selectively using a first or a second detector

In a receiving apparatus for spread spectrum communication including a plurality of correlator elements for calculating correlation values between a plurality of bits of a spread spectrum signal and a spread reference code, all the correlator elements are operated in a signal reception mode, and only a portion of the correlator elements are operated in a standby mode.

Spread spectrum receiving apparatus with battery saving function

In a spectrum spread receiver, a tracking unit tracks successive regions covering maximum correlation values, respectively, in spectrum spread demodulated components to produce a timing signal indicative of synchronous points respectively in the regions. Responsive to the timing signal, a differential demodulator unit demodulates the spectrum spread demodulated components at each synchronous point and at a time which is always one symbol period later than this synchronous point. Differential demodulation is carried out in this manner so as to be faithfully inverse relative to differential modulation in a spectrum spread transmitter.

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Tokyo, Japan

Mikio Fukushi